AK4646EN AKM [Asahi Kasei Microsystems], AK4646EN Datasheet - Page 57

• Manufacturer Part Number: AK4646EN
• Description: Stereo CODEC with MIC/SPK-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

LOVL1-0: Output Stereo Line Gain Select (Table 41)
MS0557-E-02
Addr
Addr
03H
04H
Addr
05H
BEEPL: Switch Control from MIN pin to Stereo Line Output
SPKG1-0: Speaker-Amp Output Gain Select (Table 43)
MGAIN1: MIC-Amp Gain Control (Table 19)
LOPS: Stereo Line Output Power-Save Mode
DAFIL: Filter/ALC Path Select When PMADL bit = “ 1 ” or PMADR bit = “ 1 ”
DIF1-0: Audio Interface Format (Table 16)
BCKO: BICK Output Frequency Select at Master Mode (Table 10)
PLL3-0: PLL Reference Clock Select (Table 4)
FS3-0: Sampling Frequency Select (Table 5 and Table 6.) and MCKI Frequency Select (Table 11.)
PS1-0: MCKO Output Frequency Select (Table 9)
Default: 00(0dB)
0: OFF (default)
1: ON
0: Normal Operation (default)
1: Power-Save Mode
0: ADC/Recording Path (default)
1: DAC/Playback Path
Default: “10” (Left justified)
Default: “0000” (LRCK pin)
Default: “00” (256fs)
Register Name
Signal Select 2
Register Name
Mode Control 1
Register Name
Mode Control 2
When PMLO bit is “1”, BEEPL bit is enabled. When PMLO bit is “0”, the LOUT/ROUT pins go to AVSS.
FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode.
PMDAC bit = “1”.
The SDTO pin outputs “L” with regardless of PMADL and PMADR bits when DAFIL bit = “1” and
Default
Default
Default
R/W
R/W
R/W
DAFIL
R/W
R/W
PLL3
PS1
R/W
D7
D7
D7
0
0
0
LOPS
R/W
PLL2
D6
R/W
R/W
PS0
0
D6
D6
0
0
MGAIN1
- 57 -
R/W
PLL1
D5
R/W
R/W
0
FS3
D5
D5
0
0
SPKG1
R/W
PLL0
D4
R/W
0
D4
D4
0
R
0
0
SPKG0
R/W
BCKO
D3
0
R/W
D3
D3
R
0
0
0
BEEPL
R/W
D2
R/W
FS2
0
D2
D2
R
0
0
0
LOVL1
DIF1
R/W
R/W
R/W
FS1
D1
D1
D1
0
0
1
[AK4646]
LOVL0
2007/05
DIF0
R/W
R/W
R/W
FS0
D0
D0
D0
0
0
0