CYIL1SM1300AA_09 CYPRESS [Cypress Semiconductor], CYIL1SM1300AA_09 Datasheet - Page 13

• Manufacturer Part Number: CYIL1SM1300AA_09
• Description: LUPA-1300 1.3 MPxl High Speed CMOS Image Sensor
• Manufacturer: CYPRESS [Cypress Semiconductor]

Except from Vpix power supply, drivers generate the other pixel signals on chip. The external signals to obtain the required pulses
consist of two groups. One is the group of digital signals to indicate when the pulse must occur and the other group is dc-supply lines
indicating the levels of the pulses.
Table 9. Overview of Internal and External Pixel Array Signals
The Precharge and Sample signals are the most straightforward
signals. The internal signal Vmemory is a signal that switches
between a low voltage (3.5 - 5.5V) and a high voltage (5-6V). The
signal Mem_hl controls the applied level and the power supply
lines Vmem_l and Vmem_h determine the low and high
dc-levels.
The Reset signal is due to the dual slope technique a little more
complex. In case the dual slope is not used, the reset signal is
straightforward generated from the external reset pulse. In this
case the supply voltage Vres determines the level to which the
pixel is resetted.
In case the dual slope operation is desired, one needs to give a
second pulse to a lower reset level during integration. This can
be done by the control signal Reset_ds and by the power supply
Vres_ds that defines the level to which the pixel has to be
resetted.
If a pulse is given on the Reset_ds signal, a second pulse on the
internal reset line is generated to a lower level, determined by
the supply Vres_ds. If no Reset_ds pulse is given, the dual slope
technique is not implemented.
Note that Reset is dominant over Reset_ds, which means that
the high voltage level will be applied for reset, if both pulses occur
at the same time.
The external control signals should be capable of driving input
capacitance of about 20 pF.
Digital Signals
The following digital signals control the readout of image sensor:
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Document Number: 38-05711 Rev. *D
Precharge
Sample
Reset
Vmemory
Sync_y: Starts the readout of the frame or window at the
address defined by the y-address register. This pulse synchro-
nizes the y-address register: active high. This signal is at the
same time the end of the frame or window and determines the
window width.
Clock_y: Clock of the y-register. On the rising edge of this clock,
the next line is selected.
Sync_x: Starts the readout of the selected line at the address
defined by the x-address register. This pulse synchronizes the
x-address register: active high. This signal is at the same time
the end of the line and determines the window length.
Address: the x- and y-address is downloaded serial through
this signal.
Clock_spi: clock of the serial parallel interface. This clock
downloads the address into the SPI register.
Internal Signal
0
0
0V
4.5V
Vlow
Table 9
5V
5V
4 - 6V
6V
summarizes the relation between the internal and external pixel array signals.
Vhigh
Precharge
Sample
Reset & Reset_ds
Mem_hl
External Control Signal
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All digital signals are buffered and filtered on chip to remove
spikes and achieve required on-chip driving speed. Applied
digital signals should be capable of driving 20 pF input capaci-
tance.
Test Signals
Some test signals are required to evaluate the optical perfor-
mance of the image sensor. Other test signals allow us to test
internal modules in the image sensor and some test signals will
give us information concerning temperature and influence of the
temperature on the black level.
Evaluation on optical performance (spectral response, fill factor):
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Evaluation of the output stages:
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Evaluation of the x and y -shift registers:
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Indication of the temperature and influence on the black level:
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Load_addr: when the SPI register is downloaded with the
desired address, the signal Load_addr signal loads the x-and
y-address into their address register as starting point of the
window of interest.
Sh_col: control signal of the column readout. Is only used in
sample & hold mode (see
Norow_sel: Control signal of the column readout. Is only used
in Norow_sel mode (see
Pre_col: Control signal of the column readout to reduce row
blanking time
Sel_active: activates the active load on chip for the output
amplifiers. If not used, a passive load can be used or one can
use this signal to put the output stages in standby mode
Eos_x: end of scan signal: an output signal, indicating when
end of line is reached. Is not generated when doing windowing
Eos_y: end of scan signal: is an output signal, indicating when
the end of the frame is reached. Is not generated when doing
windowing.
Array_diode
Full_diode
Black
Dc_black
Eos_x
Eos_y
Temp_diode_n
Temp_diode_p
Gnd
Gnd
Gnd_res
Vmem_l
Low DC Level
“Timing”
“Timing”
CYIL1SM1300AA
on page 14).
on page 14).
Vddr
Vddr
Vres & Vres_ds
Vmem_h
High DC Level
Page 13 of 29
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