CYIL1SM1300AA_09 CYPRESS [Cypress Semiconductor], CYIL1SM1300AA_09 Datasheet - Page 12

• Manufacturer Part Number: CYIL1SM1300AA_09
• Description: LUPA-1300 1.3 MPxl High Speed CMOS Image Sensor
• Manufacturer: CYPRESS [Cypress Semiconductor]

Biasing and Analog Signals
Besides the biasing signals, the only analog signals are the output signals Out1 - Out16. Each output signal is analog with respect to
the voltage level, but is discrete in time. This means that on the speed of Clock_x, the outputs change to a different level, depending
on the illumination of the corresponding pixels.
The biasing signals determine the speed and power dissipation of the different modules on chip. These biasing signals have to be
connected trough a resistor to ground or power supply and should be decoupled with a capacitor. If the sensor is working properly,
each of the biasing signals will have a dc-voltage depending on the resistor value and on the internal circuitry. These dc-voltages can
be used to check the operation of the image sensor.
and the expected dc-voltage. Due to small process variations, these dc-voltages change from chip to chip and 10% variation is
possible.
Table 8. Overview of Biasing Signals
Each resistor controls the speed and power dissipation of the corresponding module, as this resistor determines the current required
to charge and/or discharge internal nodes inside the module.
A decoupling with a small capacitor is advisable to reduce the HF noise onto the analog signals. Only the capacitor on the Pre_load
signal can be omitted.
Pixel Array Signals
Figure 4
Precharge, Vmemory, row select and Vpix. These are internal generated signals derived by on-chip drivers from external applied
signals. Consequently it is important to understand the relation between both internal and external signals and to understand the
operation of the pixel.
The timing of the pixel is given in
At the end of the integration time, the information on the photodiode node needs to be sampled and stored onto the pixel memory,
required to allow synchronous shutter. To do this, we need the signals "Precharge" and "Sample". "Precharge" resets the pixel memory
and "Sample" places the pixel information onto the pixel memory. Once this information stored, the readout of the pixel memories can
start in parallel with a new integration time. An additional signal "Vmem" is needed to obtain a larger output swing.
Document Number: 38-05711 Rev. *D
Pre_load
Col_load
Psf_load
Nsf_load
Load_out
Decx_load
Decy_load
is a schematic representation of the pixel as used in the LUPA design. The applied signals to this pixel are: reset, sample,
Signal
Connect with 100 KΩ to Vdda and capacitor of 100 nF to Gnd
Connect with 10 KΩ to Vdda and capacitor of 100 nF to Gnd
Connect with 2 MΩ to Vdda and capacitor of 100 nF to Gnd
Connect with 240 KΩ to Gnd and capacitor of 100 nF to Vdda
Connect with 27 KΩ to Voo and capacitor of 100 nF to Gnd
Connect with 27 KΩ to Gnd and capacitor of 100 nF to Vdd
Connect with 27 KΩ to Gnd and capacitor of 100 nF to Vdd
Figure 12
in which only the internal signals are given.
Figure 12. Internal Timing of the Pixel
Table 8
Comment
gives the different biasing signals, the way they should be connected,
CYIL1SM1300AA
Expected DC Level
2.8V
2.8V
2.0V
0.9V
3.7V
1.3V
1.6V
Page 12 of 29
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