LXT972 Level One, LXT972 Datasheet - Page 8

• Manufacturer Part Number: LXT972
• Description: 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
• Manufacturer: Level One

LXT972 3.3V Dual-Speed Fast Ethernet Transceiver
Table 4:
8
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain
LQFP
9, 10,
Pin#
12
17
33
34
35
39
44
5
6
4
1
2
TxSLEW0
TxSLEW1
RESET
ADDR0
RBIAS
PAUSE
TEST0
TEST1
PWRDWN
REFCLK/XI
XO
N/C
LXT972 Miscellaneous Signal Descriptions
Symbol
Type
AI
O
I
I
I
I
I
I
I
I
-
1
Tx Output Slew Controls 0 and 1. These pins select the TX output slew rate
(rise and fall time) as follows:
TxSLEW1
Reset. This active Low input is OR’ed with the control register Reset bit (0.15).
The LXT972 reset cycle is extended to 258 s (nominal) after reset is deas-
serted.
Address0. Sets device address.
Bias. This pin provides bias current for the internal circuitry. Must be tied to
ground through a 22.1 k , 1% resistor.
Pause. When set High, the LXT972 advertises Pause capabilities during auto
negotiation.
Test. Tie Low.
Test. Tie Low.
Power Down. When set High, this pin puts the LXT972 in a power-down
mode.
Crystal Input and Output. A 25 MHz crystal oscillator circuit can be con-
nected across XI and XO. A clock can also be used at XI. Refer to Functional
Description for detailed clock requirements.
No Connection. These pins are not used and should not be terminated.
0
0
1
1
TxSLEW0
0
1
0
1
Signal Description
Slew Rate (Rise and Fall Time)
2.5 ns
3.1 ns
3.7 ns
4.3 ns