LXT972 Level One, LXT972 Datasheet - Page 13

• Manufacturer Part Number: LXT972
• Description: 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
• Manufacturer: Level One

Figure 4: Interrupt Logic
1. Interrupt (Event) Status Register is cleared on read.
MII Interrupts
Force Interrupt
Event X Mask Reg
Event X Status Reg
The LXT972 provides a single interrupt pin (MDINT).
Interrupt logic is shown in
provides two dedicated interrupt registers. Register 18
provides interrupt enable and mask functions and Reg-
ister 19 provides interrupt status. Setting bit 18.1 = 1,
enables the device to request interrupt via the MDINT
pin. An active Low on this pin indicates a status
change on the LXT972. Interrupts may be caused by
four conditions:
• Auto-negotiation complete
• Speed status change
• Duplex status change
• Link status change
Per Event
. .
.
AND
Figure
4. The LXT972 also
Interrupt Enable
OR
NAND
Hardware Control Interface
The LXT972 provides a Hardware Control Interface
for applications where the MDIO is not desired. The
Hardware Control Interface uses the three LED driver
pins to set device configuration.
Hardware Configuration Settings section on page 16
for additional details.
Interrupt Pin
LXT972 Functional Description
(MDINT)
Refer to the
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