LXT972 Level One, LXT972 Datasheet - Page 27

• Manufacturer Part Number: LXT972
• Description: 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
• Manufacturer: Level One

PMA Sublayer
Link
In 100 Mbps mode, the LXT972 establishes a link
whenever the scrambler becomes locked and remains
locked for approximately 50 ms.
scrambler loses lock (receiving less than 12
consecutive idle symbols during a 2 ms window), the
link will be taken down. This provides a very robust
link, essentially filtering out any small noise hits that
may otherwise disrupt the link. Furthermore 100M
idle patterns will not bring up a 10M link.
The LXT972 reports link failure via the MII status
bits (1.2 and 17.10) and interrupt functions. If auto-
negotiation is enabled, link failure causes the LXT972
to re-negotiate.
Link Failure Override
The LXT972 will normally transmit data packets only
if it detects the link is up. Setting bit 16.14 = 1
overrides this function, allowing the LXT972 to
transmit data packets even when the link is down.
This feature is provided as a diagnostic tool. Note that
auto-negotiation must be disabled to transmit data
packets in the absence of link. If auto-negotiation is
enabled, the LXT972 will automatically transmit FLP
bursts if the link is down.
Carrier Sense
For 100TX links, a start-of-stream delimiter (SSD) or
/J/K symbol pair causes assertion of carrier sense
(CRS). An end-of-stream delimiter (ESD) or /T/R
symbol pair causes de-assertion of CRS. The PMA
layer will also de-assert CRS if IDLE symbols are
received without /T/R; however, in this case RX_ER
will be asserted for one clock cycle when CRS is de-
asserted.
Usage of CRS for Interframe Gap (IFG) timing is not
recommended for the following reasons:
Receive Data Valid
The LXT972 asserts RX_DV to indicate that the
received data maps to valid symbols. However, RXD
outputs zeros until the received data is decoded and
available for transfer to the controller.
• De-assertion time for CRS is slightly longer than
• CRS de-assertion is not aligned with TX_EN de-
assertion time.
appear somewhat shorter to the MAC than it
actually is on the wire.
assertion on transmit loopbacks in half-duplex
mode.
This causes IFG intervals to
Whenever the
Twisted-Pair PMD Sublayer
The twisted-pair Physical Medium Dependent (PMD)
layer
descrambling, line coding and decoding (MLT-3 for
100TX, Manchester for 10T), as well as receiving,
polarity correction, and baseline wander correction
functions.
Scrambler/Descrambler
The purpose of the scrambler is to spread the signal
power spectrum and further reduce EMI using an
11-bit, data-independent polynomial. The receiver
automatically decodes the polynomial whenever
IDLE symbols are received.
Scrambler Seeding. Once the transmit data (or Idle
symbols) are properly encoded, they are scrambled to
further reduce EMI and to spread the power spectrum
using an 11-bit scrambler seed. Five seed bits are
determined by the PHY address, and the remaining
bits are hard coded in the design.
Scrambler Bypass. The scrambler/descrambler can
be bypassed by setting bit 16.12 = 1. Scrambler
bypass is provided for diagnostic and test support.
Baseline Wander Correction
The LXT972 provides a baseline wander correction
function which makes the device robust under all
network operating conditions.
scheme used in 100BASE-TX is by definition
“unbalanced”. This means that the average value of
the signal voltage can “wander” significantly over
short time intervals (tenths of seconds). This wander
can cause receiver errors at long-line lengths (100
meters) in less robust designs. Exact characteristics of
the wander are completely data dependent.
The
characteristics allow the device to recover error-free
data while receiving worst-case “killer” packets over
all cable lengths.
Polarity Correction
The 100BASE-TX descrambler automatically detects
and corrects for the condition where the receive signal
at TPIP and TPIN is inverted.
Programmable Slew Rate Control
The LXT972 device supports a slew rate mechanism
whereby one of four pre-selected slew rates can be
used. This allows the designer to optimize the output
waveform to match the characteristics of the
magnetics.
TxSLEW pins as shown in
LXT972
provides
LXT972 Functional Description
The slew rate is determined by the
the
baseline
signal
Table 4 on page
wander
The MLT3 coding
scrambling
correction
8.
and
27