LXT972 Level One, LXT972 Datasheet - Page 18

• Manufacturer Part Number: LXT972
• Description: 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
• Manufacturer: Level One

LXT972 3.3V Dual-Speed Fast Ethernet Transceiver
MII Operation
The LXT972 device implements the Media Independent
Interface (MII) as defined in the IEEE 802.3 standard.
Separate channels are provided for transmitting data from
the MAC to the LXT972 (TXD), and for passing data
received from the line (RXD) to the MAC. Each channel
has its own clock, data bus, and control signals. Nine
signals are used to pass received data to the MAC:
RXD<3:0>, RX_CLK, RX_DV, RX_ER, COL, and CRS.
Seven signals are used to transmit data from the MAC:
TXD<3:0>, TX_CLK, TX_EN, and TX_ER.
The LXT972 supplies both clock signals as well as separate
outputs for carrier sense and collision. Data transmission
across the MII is normally implemented in 4-bit-wide
nibbles.
MII Clocks
The LXT972 is the master clock source for data
transmission and supplies both MII clocks (RX_CLK and
TX_CLK). It automatically sets the clock speeds to match
link conditions. When the link is operating at 100 Mbps,
the clocks are set to 25 MHz. When the link is operating at
10 Mbps, the clocks are set to 2.5 MHz.
10
and control signals must always be synchronized to
TX_CLK by the MAC. The LXT972 samples these signals
on the rising edge of TX_CLK.
Transmit Enable
The MAC must assert TX_EN the same time as the first
nibble of preamble, and de-assert TX_EN after the last bit
of the packet.
Receive Data Valid
The LXT972 asserts RX_DV when it receives a valid
packet. Timing changes depend on line operating speed:
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• For 100TX links, RX_DV is asserted from the first
• For 10BT links, the entire preamble is truncated.
show the clock cycles for each mode. The transmit data
nibble of preamble to the last nibble of the data
packet.
RX_DV is asserted with the first nibble of the Start of
Frame Delimiter (SFD) “5D” and remains asserted
until the end of the packet.
Figures 8 through
Carrier Sense
Carrier sense (CRS) is an asynchronous output. It is always
generated when a packet is received from the line and in
half-duplex when a packet is transmitted.
Carrier sense is not generated when a packet is transmitted
and in full-duplex mode.
conditions for assertion of carrier sense, collision, and data
loopback signals.
Error Signals
When LXT972 is in 100 Mbps mode and receives an
invalid symbol from the network, it asserts RX_ER and
drives “1110” on the RXD pins.
When the MAC asserts TX_ER, the LXT972 will drive
“H” symbols out on the TPOP/N pins.
Collision
The LXT972 asserts its collision signal, asynchronously to
any clock, whenever the line state is half-duplex and the
transmitter and receiver are active at the same time.
summarizes the conditions for assertion of carrier sense,
collision, and data loopback signals.
Table 9
summarizes the
Table 9