LXT972 Level One, LXT972 Datasheet

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... Robust baseline wander correction performance. • Standard CSMA/CD or full-duplex operation. • Configurable via MDIO serial port or hardware control pins. • Integrated, programmable LED drivers. • 64-pin Low-profile Quad Flat Package (LQFP). • LXT972LC - Commercial ( ambient). Register Set Clock Generator Manchester 1 0 ...

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... LXT972 3.3V Dual-Speed Fast Ethernet Transceiver Pin Assignments .........................................................4 Signal Descriptions......................................................6 Functional Description..............................................10 Introduction...............................................................10 OSP™ Architecture ................................................10 Comprehensive Functionality................................11 Network Media/Protocol Support 10/100 Network Interface ......................................11 Twisted-Pair Interface.......................................11 Fault Detection and Reporting Remote Fault................................................11 MII Data Interface ...................................................12 Configuration Management Interface MDIO Management Interface..........................12 MDIO Addressing ...

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... Quick Status Register (Address 17) ...................... 31 Interrupt Enable Register (Address Interrupt Status Register (Address LED Configuration Register (Address 20) Transmit Control Register (Address Package Specifications Revision History Pins.................... .................... 38 39 .......... 40 ......... 41 ........................ 44 .... 45 ........ 47 .......... 53 .......... 53 4)............ 54 .... 55 LXT972 Table of Contents ..............................................................56 ..............................................................57 16)...........58 ....................59 18)...............60 19)................61 ..........62 30)..............64 ............................................65 .........................................................66 ..57 3 ...

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... LXT972 3.3V Dual-Speed Fast Ethernet Transceiver Figure 1: 64-Pin LQFP Pin Assignments REFCLK/ MDDIS 3 RESET 4 TXSLEW0 5 TXSLEW1 6 GND 7 VCCIO 8 N/C 9 N/C 10 GND 11 ADDR0 12 GND 13 GND 14 GND 15 GND 16 4 PIN ASSIGNMENTS LXT972 48 RXD0 RXD1 47 RXD2 46 45 RXD3 44 N/C 43 MDC 42 MDIO 41 GND VCCIO 40 39 PWRDWN ...

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... Table 6 on page 9 63. CRS Table 6 on page 9 64. MDINT Table 6 on page 9 Table 6 on page 9 Table 5 on page 9 Table 4 on page 8 LXT972 Pin Assignments LQFP Numeric Pin List – continued Reference for Type Full Description Input Table 4 on page 8 Input ...

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... RXD1 48 RXD0 49 RX_DV O Receive Data Valid. The LXT972 asserts this signal when it drives valid data on RXD. This output is synchronous to RX_CLK. 53 RX_ER O Receive Error. Signals a receive error condition has occurred. This output is synchronous to RX_CLK. Transmit Error. Signals a transmit error condition. This signal must be ...

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... Management Data Input/Output. Bidirectional serial data channel for PHY/STA communication. 64 MDINT OD Management Data Interrupt. When bit 18 active Low output on this pin indicates status change. Interrupt is cleared by reading Register 19. 1. Type Column Coding Input Output Analog Open Drain. Table 3: LXT972 Network Interface Signal Descriptions LQFP 1 Symbol Type Pin# 19 TPOP O ...

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... Reset. This active Low input is OR’ed with the control register Reset bit (0.15). The LXT972 reset cycle is extended to 258 s (nominal) after reset is deas- serted. Address0. Sets device address. Bias. This pin provides bias current for the internal circuitry. Must be tied to ground through a 22 ...

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... Table 5: LXT972 Power Supply Signal Descriptions LQFP Symbol Type Pin# 51 VCCD - 7, 11, 13, GND - 14, 15, 16, 18, 25, 26, 32, 41, 50 VCCIO - 21, 22 VCCA - Table 6: LXT972 JTAG Test Signal Descriptions LQFP 1 Symbol Type Pin TDI TDO TMS TCK TRST 1 ...

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... The LXT972 is a single-port Fast Ethernet 10/100 Transceiver that supports 10 Mbps and 100 Mbps networks. It complies with all applicable requirements of IEEE 802.3. The LXT972 can directly drive either a 100BASE-TX line (up to 140 meters 10BASE-T line (up to 185 meters). Comprehensive Functionality The LXT972 provides a standard Media Independent Interface (MII) for 10/100 MACs ...

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... Only a transformer, RJ-45 connector, load resistor, and bypass capacitors are required to complete this interface. On the transmit side, the LXT972 has an active internal termination and does not require exter- nal termination resistors. Level One's patented wave- shaping technology shapes the outgoing signal to help reduce the need for external EMI filters ...

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... Refer to “MII Operation” on page 18 additional details. Configuration Management Interface The LXT972 provides both an MDIO interface and a Hardware Control Interface for device configuration and management. MDIO Management Interface The LXT972 supports the IEEE 802.3 MII Management ...

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... Reg- ister 19 provides interrupt status. Setting bit 18 enables the device to request interrupt via the MDINT pin. An active Low on this pin indicates a status change on the LXT972. Interrupts may be caused by four conditions: • Auto-negotiation complete • Speed status change • ...

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... MHz. Refer to page 46 for details. Initialization When the LXT972 is first powered on, reset, or encounters a link failure state, it checks the MDIO register configuration bits to determine the line speed and operating conditions to use for the network link. The configuration bits may be set by the Hardware Control or MDIO interface ...

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... The hardware power-down mode is controlled by the PWRDWN pin. When PWRDWN is High, the follow- ing conditions are true: • The LXT972 network port and clock are shut down. • All outputs are tri-stated. • All weak pad pull-up and pull-down resistors are disabled. • ...

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... LXT972 3.3V Dual-Speed Fast Ethernet Transceiver Hardware Configuration Settings The LXT972 provides a hardware option to set the initial device configuration. The hardware option uses the three LED driver pins. This provides three control bits, as listed in Table 8. The LED drivers can operate as either open- drain or open-source circuits as shown in ...

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... FLP burst exchanges 16 bits of data, which are referred “link code word”. All devices that support auto- negotiation must implement the “Base Page” defined by IEEE 802.3 (registers 4 and 5). LXT972 also supports the optional “Next Page” function as described in and 45 (registers 7 and 8) ...

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... Error Signals When LXT972 is in 100 Mbps mode and receives an invalid symbol from the network, it asserts RX_ER and drives “1110” on the RXD pins. When the MAC asserts TX_ER, the LXT972 will drive “ ...

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... LXT972) XI 2.5 MHz during Auto-Negotiation and 10BASE-T Data & Idle 2.5 MHz during Auto-Negotiation and 10BASE-T Data & Idle Constant 25 MHz 2.5 MHz during Auto-Negotiation 2.5 MHz during Auto-Negotiation Constant 25 MHz LXT972 Functional Description 25 MHz once 100BASE-X Link Established 25 MHz once 100BASE-X Link Established 19 ...

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... Test Loopback A test loopback function is provided for diagnostic testing of the LXT972. During test loopback, the twisted-pair interface is disabled. Data transmitted by the MAC is internally looped back by the LXT972 and returned to the MAC. Table 9: Carrier Sense, Loopback, and Collision Conditions Speed Duplex Condition ...

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... Start-of-Frame /J/K/ code-groups Delimiter (SFD) Start-of-Stream Delimiter (SSD 100TX mode, the LXT972 scrambles and transmits the Figure 12 data to the network using MLT-3 line code page 22). MLT-3 signals received from the network are descrambled, decoded, and sent across the MII to the MAC ...

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... LXT972 3.3V Dual-Speed Fast Ethernet Transceiver Figure 13: 100BASE-TX Data Path Standard Data Flow Parallel D0 to Serial Serial to D3 Parallel Scrambler Bypass Data Flow S0 Parallel to S1 Serial S2 Serial S3 to Parallel S4 22 Scramble 4B/5B Scramble MLT3 De- Transition = 1 ...

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... Figure 12 on page 21, the MAC starts each transmission with a preamble pattern. As soon as the LXT972 detects the start of preamble, it transmits a Start- of-Stream Delimiter (SSD, symbols J and K) network. It then encodes and transmits the rest of the packet, including the balance of the preamble, the SFD, packet data, and CRC ...

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... LXT972 3.3V Dual-Speed Fast Ethernet Transceiver Collision Indication Figure 16 shows normal transmission. Upon detection of a collision, the COL output is asserted and remains asserted for the duration of the collision as shown in Figure 16: 100BASE-TX Transmission with no Errors TXD<3:0> ...

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... Protocol Sublayer Operations With respect to the 7-layer communications model, the LXT972 is a Physical Layer 1 (PHY) device. The LXT972 implements the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), and Physical Medium Dependent (PMD) sublayers of the reference model defined by the IEEE 802.3u standard. ...

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... LXT972 3.3V Dual-Speed Fast Ethernet Transceiver Table 10: 4B/5B Coding 4B Code Code Type DATA ...

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... PMA Sublayer Link In 100 Mbps mode, the LXT972 establishes a link whenever the scrambler becomes locked and remains locked for approximately 50 ms. scrambler loses lock (receiving less than 12 consecutive idle symbols during window), the link will be taken down. This provides a very robust link, essentially filtering out any small noise hits that may otherwise disrupt the link ...

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... LXT972 are the SFD “5D” hex followed by the body of the packet. In 10T mode with 16 the LXT972 passes the preamble through the MII and asserts RX_DV and CRS simultaneously. In 10T loopback, the LXT972 loops back whatever the MAC transmits to it, including the preamble ...

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... Bits 17.14 and 17.9 can be used to determine the link operating conditions (speed and duplex). Monitoring Next Page Exchange The LXT972 offers an Alternate Next Page mode to simplify the next page exchange process. Normally, bit 6.1 (Page Received) remains set until read. When Alternate Next Page mode is enabled (16.1 = 1), bit 6 ...

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... LXT972 3.3V Dual-Speed Fast Ethernet Transceiver The LED driver pins also provide initial configuration settings. The LED pins are sensitive to polarity and will automatically pull up or pull down to configure for either open drain or open source circuits (10 mA Max current rating) as required by the hardware configuration. Refer to the discussion of “ ...

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... Boundary Scan (JTAG1149.1) Functions LXT972 includes a IEEE 1149.1 boundary scan test port for board level testing. All digital input, output, and input/ output pins are accessible. The BSDL file is available by contacting your local sales office (see the back page accessing the Level One website (www.level1.com). ...

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... LXT972 3.3V Dual-Speed Fast Ethernet Transceiver APPLICATION INFORMATION Magnetics Information The LXT972 requires a 1:1 ratio for both the receive and transmit transformers. The transformer isolation voltage should be rated protect the circuitry from static voltages across the connectors and cables. Refer to Table 14 for transformer requirements ...

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... A separate ferrite bead (rated at 50 mA) should be used to supply center-tap current. 2. The 100 transmit load termination resistor typically required is integrated in the LXT972. 3. Magnetics without a receive pair center-tap do not require termination. 4. RJ-45 connections shown are for a standard switch application. For a standard NIC RJ-45 setup, see Figure 21 ...

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... A separate ferrite bead (rated at 50 mA) should be used to supply center-tap current. 2. The 100 transmit load termination resistor typically required is integrated in the LXT972. 3. Magnetics without a receive pair center-tap do not require termination. 4. RJ-45 connections shown are for a standard NIC. Tx/Rx crossover may be required for repeater & switch applications ...

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... Figure 22: Typical MII Interface MAC TX_EN TX_ER TXD<3:0> TX_CLK RX_CLK LXT972 RX_DV RX_ER RXD<3:0> CRS COL LXT972 Application Information X F RJ- ...

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... Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. Voltages with respect to ground unless otherwise specified. 36 NOTE Figures 23 through 34 represent the target specifications of the LXT972. apply over the recommended operating conditions specified in Sym V CC ...

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... Input Clock Frequency Tolerance 2 Input Clock Duty Cycle Input Capacitance 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. Parameter is guaranteed by design; not subject to production testing. LXT972 Preliminary Test Specifications 1 2 Min Max Typ – ...

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... LXT972 3.3V Dual-Speed Fast Ethernet Transceiver Table 21: I/O Characteristics - LED/CFG Pins Parameter Output Low Voltage Output High Voltage Input Current Table 22: 100BASE-TX Transceiver Characteristics Parameter Peak differential output voltage Signal amplitude symmetry Signal rise/fall time Rise/fall time symmetry Duty cycle distortion Overshoot/Undershoot Jitter (measured differentially) 1. Typical values are at 25 ° ...

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... Link Min Receive Timer T Link Max Receive Timer T Link Transmit Period Link Pulse Width 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. LXT972 Preliminary Test Specifications Sym Min Typ T 50 – ...

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... LXT972 3.3V Dual-Speed Fast Ethernet Transceiver Timing Diagrams Figure 23: 100BASE-TX Receive Timing - 4B Mode TPI < > Table 25: 100BASE-TX Receive Timing Parameters - 4B Mode Parameter RXD<3:0>, RX_DV, RX_ER setup to RX_CLK High RXD<3:0>, RX_DV, RX_ER hold from RX_CLK High CRS asserted to RXD< ...

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... Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 100BASE-T bit time = 10 LXT972 Preliminary Test Specifications t1 ...

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... LXT972 3.3V Dual-Speed Fast Ethernet Transceiver Figure 25: 10BASE-T Receive Timing TPI Table 27: 10BASE-T Receive Timing Parameters Parameter RXD, RX_DV, RX_ER Setup to RX_CLK High RXD, RX_DV, RX_ER Hold from RX_CLK ...

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... Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 10BASE-T bit time = 10 LXT972 Preliminary Test Specifications t ...

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... LXT972 3.3V Dual-Speed Fast Ethernet Transceiver Figure 27: 10BASE-T Jabber and Unjabber Timing Table 29: 10BASE-T Jabber and Unjabber Timing Parameters Parameter Maximum transmit time Unjab time 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. ...

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... Clock pulse to Clock pulse FLP burst width FLP burst to FLP burst Clock/Data pulses per burst 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. LXT972 Preliminary Test Specifications Data Pulse ...

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... LXT972 3.3V Dual-Speed Fast Ethernet Transceiver Figure 31: MDIO Input Timing Figure 32: MDIO Output Timing Table 32: MDIO Timing Parameters Parameter MDIO setup before MDC, sourced by STA MDIO hold after MDC, sourced by STA MDC to MDIO output delay, source by PHY MDC period 1. Typical values are at 25° ...

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... Reset Recovery Delay is specified as a maximum value because it refers to the PHY's guaranteed performance - the PHY will come out of reset after a delay of No MORE Than 300 s should delay No LESS Than 300 before accessing the MDIO port. LXT972 Preliminary Test Specifications v1 1 Sym Min ...

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... LXT972 3.3V Dual-Speed Fast Ethernet Transceiver The LXT972 register set includes multiple 16-bit registers. Refer to Table 35 for a complete register listing. • Base registers (0 through 8) are defined in accordance with the “Reconciliation Sublayer and Media Independent Interface” and “Physical Layer Link Signaling for 10/100 Mbps Auto-Negotiation” ...

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Table 36: Register Bit Map Reg Title B15 B14 B13 B12 B11 Speed A/N Power Control Reset Loopback Select Enable Down 100Base- 100Base- 10Mbps 10Mbps 100Base- Status X Full X Half Full Half T4 Duplex Duplex Duplex Duplex PHY ID ...

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Table 36: Register Bit Map – continued Reg Title B15 B14 B13 B12 B11 Status 10/100 Transmit Receive Collision Reserved Register #2 Mode Status Status Status Interrupt Reserved Enable Interrupt Reserved Status LED Config LED1 Trans. Transmit Port Rise Time ...

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... Reserved 1 0 1000 Mbps (not supported 100 Mbps Mbps 0.13 Speed Selected 1 1 Reserved 1 0 1000 Mbps (not supported 100 Mbps Mbps LXT972 Register Definitions 1 Type R/W SC R/W R/W R/W R/W R/W R/W SC R/W R/W R/W R/W Table 8 on page 16). Default 0 0 Note 2 Note Note 2 ...

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... LXT972 3.3V Dual-Speed Fast Ethernet Transceiver Table 38: MII Status Register #1 (Address 1) Bit Name 1.15 100BASE- PHY able to perform 100BASE- PHY not able to perform 100BASE-T4 Not Supported 1.14 100BASE-X Full PHY able to perform full-duplex 100BASE-X Duplex 0 = PHY not able to perform full-duplex 100BASE-X 1.13 100BASE-X Half PHY able to perform half-duplex 100BASE-X ...

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... The Level One OUI is 00207B hex Description Description LXT972 Register Definitions 1 Default Type RO 0013 hex 1 Type Default RO 011110 RO 001110 RO 0001 x PHY ID Register #2 (Address 3) ...

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... Pause operation enabled for full-duplex links Pause operation disabled. 4.9 100BASE- 100BASE-T4 capability is available 100BASE-T4 capability is not available. (The LXT972 does not support 100BASE-T4 but allows this bit to be set to advertise in the Auto-Negotiation sequence for 100BASE-T4 operation. An external 100BASE-T4 transceiver could be switched in if this capability is desired.) 4.8 100BASE- Port is 100BASE-TX full-duplex capable ...

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... Next Page 1 = Link Partner has ability to send multiple pages Link Partner has no ability to send multiple pages. 5.14 Acknowledge 1 = Link Partner has received Link Code Word from LXT972 Link Partner has not received Link Code Word from the LXT972. 5.13 Remote Fault 1 = Remote fault. ...

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... LXT972 3.3V Dual-Speed Fast Ethernet Transceiver Table 43: Auto Negotiation Expansion (Address 6) Bit Name 6.15:6 Reserved Ignore on read. 6.5 Base Page This bit indicates the status of the Auto-Negotiation variable, base page. It flags synchronization with the Auto-Negotiation state dia- gram allowing detection of interrupted links. This bit is only used if bit 16 ...

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... Link Partner has no additional next pages to send 8.14 Acknowledge 1 = Link Partner has received Link Code Word from LXT972 (ACK Link Partner has not received Link Code Word from LXT972 8.13 Message Page 1 = Page sent by the Link Partner is a Message Page (MP Page sent by the Link Partner is an Unformatted Page 8 ...

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... LXT972 3.3V Dual-Speed Fast Ethernet Transceiver Table 46: Configuration Register (Address 16, Hex 10) Bit Name 16.15 Reserved Write as zero, ignore on read. 16.14 Force Link Pass 1 = Force Link pass 0 = Normal operation 16.13 Transmit Disable 1 = Disable Twisted Pair transmitter 0 = Normal Operation 16.12 Bypass Scrambler 1 = Bypass Scrambler and Descrambler (100BASE-TX Normal Operation 16 ...

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... Name 17.15 Reserved Always 0. 17.14 10/100 Mode 1 = LXT972 is operating in 100BASE-TX mode LXT972 is not operating 100BASE-TX mode. 17.13 Transmit Status 1 = LXT972 is transmitting a packet LXT972 is not transmitting a packet. 17.12 Receive Status 1 = LXT972 is receiving a packet LXT972 is not receiving a packet. 17.11 Collision Status 1 = Collision is occurring collision. 17.10 Link 1 = Link is up. ...

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... LXT972 3.3V Dual-Speed Fast Ethernet Transceiver Table 48: Interrupt Enable Register (Address 18) Bit Name 18.15:9 Reserved Write as 0; ignore on read. 18.8 Reserved Write as 0; ignore on read. 18.7 ANMSK Mask for Auto Negotiate Complete 1 = Enable event to cause interrupt not allow event to cause interrupt. 18.6 SPEEDMSK Mask for Speed Interrupt 1 = Enable event to cause interrupt ...

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... A Link Change has occurred since last reading this register Link Change has not occurred since last reading this register. 19.3 Reserved Ignore 19.2 MDINT 1 = MII interrupt pending MII interrupt pending. 19.1 Reserved Ignore. 19.0 Reserved Ignore 1. R/W = Read/Write Self Clearing. LXT972 Register Definitions Description 1 Default Type RO N RO/SC N/A RO/SC 0 RO/SC 0 RO/SC ...

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... LXT972 3.3V Dual-Speed Fast Ethernet Transceiver Table 50: LED Configuration Register (Address 20, Hex 14) Bit Name 20.15:12 LED1 0000 = Display Speed Status (Continuous, Default) 0001 = Display Transmit Status (Stretched) Programming 0010 = Display Receive Status (Stretched) bits 0011 = Display Collision Status (Stretched) 0100 = Display Link Status (Continuous) ...

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... Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full duplex. Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs. 5. Values are relative approximations. Not guaranteed or production tested. LXT972 Register Definitions – continued Description ...

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... LXT972 3.3V Dual-Speed Fast Ethernet Transceiver Table 51: Transmit Control Register #2 (Address 30) Bit Name 30.15:11 Reserved 30.12 Transmit Low Power 30.11:10 Port Rise Time 1 Control 30.9:0 Reserved 1. Values are relative approximations. Not guaranteed or production tested. 2. R/W = Read/Write 64 Description Ignore 1 = Forces the transmitter into low power mode. Also forces a zero-differential transmission. ...

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... PACKAGE SPECIFICATION Figure 36: LXT972 LQFP Package Specifications • Part Number - LXT972LC Commercial Temperature Range (0ºC to +70ºC) Millimeters Dim Min Max A – 1.60 A 0.05 0. 1.35 1. 0.17 0.27 D 11.85 12.15 D 9.9 10 11.85 12.15 E1 9.9 10.1 e 0.50 BSC L 0.45 0.75 L 1.00 REF Basic Spacing between Centers 64-Pin Low Profile Quad Flat Pack ...

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... LXT972 3.3V Dual-Speed Fast Ethernet Transceiver Table 52: Changes from Rev 1.0 to Rev 1.1 (02/00) Section Page Table 2 6 LXT972 MII Signal Description Twisted-Pair Interface 11 MDIO Management 12 Interface Figure 5 14 Initialization Sequence Figure 8 19 10BASE-T Clocking Figure 9 19 10BASE-X Clocking Figure 21 20 Typical TP Interface - Switch Figure 22 ...

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... NOTES LXT972 Notes 67 ...

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... Information in this document is provided in connection with Level One products. No license, express or implied, by estoppel or otherwise, to any intellectual prop- erty rights is granted by this document. Except as provided in Level One's Terms and Conditions of Sale for such products, Level One assumes no liability what- soever, and Level One disclaims any express or implied warranty, relating to sale and/or use of Level One products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right ...