EVAL-ADN2804EB AD [Analog Devices], EVAL-ADN2804EB Datasheet - Page 23

• Manufacturer Part Number: EVAL-ADN2804EB
• Description: 622 Mbps Clock and Data Recovery IC with Integrated Limiting Amplifier
• Manufacturer: AD [Analog Devices]

DC-COUPLED APPLICATION
The inputs to the ADN2804 can also be dc-coupled. This may
be necessary in burst mode applications, where there are long
periods of CIDs, and baseline wander cannot be tolerated. If the
inputs to the ADN2804 are dc-coupled, care must be taken not
to violate the input range and common-mode level require-
ments of the ADN2804 (see Figure 27 through Figure 29). If dc
coupling is required and the output levels of the TIA do not
adhere to the levels shown in Figure 28, level shifting must be
performed and/or an attenuator must be placed between the
TIA outputs and the ADN2804 inputs.
VCC
V
V
VTH = ADN2804 QUANTIZER THRESHOLD
NOTES:
1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS ZERO.
2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE
3. WHEN THE BURST OF DATA STARTS AGAIN, THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO
4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2804. THE
V1b
V2b
DIFF
DIFF
V1
V2
VREF LEVEL, WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS.
THE INPUT LEVELS CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES,
EITHER HIGH OR LOW DEPENDING ON THE LEVELS OF V1AND V1b WHEN THE TIA WENT TO CID, IS CANCELED OUT. THE QUANTIZER
DOES NOT RECOGNIZE THIS AS A VALID STATE.
QUANTIZER CAN RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT.
TIA
= V2–V2b
Figure 27. DC-Coupled Application
1
0.1µF
VCC
50Ω
50Ω
TIA
NIN
PIN
VREF
50Ω
ADN2804
50Ω
V1b
V1
3kΩ
C
C
IN
IN
2
V2b
V2
2.5V
PIN
NIN
Figure 26. Example of Baseline Wander
50Ω
50Ω
ADN2804
V
REF
Rev. 0 | Page 23 of 24
+
–
LIMAMP
3
CDR
Figure 29. Maximum Allowed DC-Coupled Input Levels
Figure 28. Minimum Allowed DC-Coupled Input Levels
NIN
PIN
PIN
NIN
C
C
OUT
OUT
DATAOUTP
DATAOUTN
V p-p = PIN – NIN = 2
V p-p = PIN – NIN = 2
4
×
×
V
V
SE
SE
= 10mV AT SENSITIVITY
= 2.0V MAX
V
V
SE
V
(DC-COUPLED)
SE
VREF
VTH
CM
V
(DC-COUPLED)
= 1.0V MAX
CM
= 5mV MIN
= 2.3V
ADN2804
= 2.3V MIN