EVAL-ADN2804EB AD [Analog Devices], EVAL-ADN2804EB Datasheet - Page 10

• Manufacturer Part Number: EVAL-ADN2804EB
• Description: 622 Mbps Clock and Data Recovery IC with Integrated Limiting Amplifier
• Manufacturer: AD [Analog Devices]

ADN2804
I
2
C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
SDA
SCK
START BIT
S
S = START BIT
A(S) = ACKNOWLEDGE BY SLAVE
S
SLAVE ADDR, LSB = 0 (WR)
A6
SLAVE ADDRESS
SDA
SCK
A5
S
t
SLADDR[4...0]
F
S
SLAVE ADDR, LSB = 0 (WR) A(S)
t
LOW
t
MSB = 1
HD;STA
1
A(S)
t
SET BY
PIN 19
SLAVE ADDRESS [6...0]
HD;DAT
SUB ADDR
t
R
A5
WR
t
SU;DAT
Figure 7. Slave Address Configuration
Figure 10. I
Figure 11. I
P = STOP BIT
A(M) = ACKNOWLEDGE BY MASTER
Figure 8. I
Figure 9. I
0
ACK
A(S)
Rev. 0 | Page 10 of 24
t
SUB ADDR
SUB ADDRESS
S
HIGH
t
2
2
2
2
F
C Data Transfer Timing
C Port Timing Diagram
C Write Data Transfer
0
C Read Data Transfer
A7
SLAVE ADDR, LSB = 1 (RD)
SUB ADDR[6...1]
t
SU;STA
0
A(S)
DATA
0
S
A0
A(S)
A(M) = LACK OF ACKNOWLEDGE BY MASTER
t
SU;STO
0
A(S) DATA A(M)
t
HD;STA
ACK
0 = WR
1 = RD
R/W
CTRL.
DATA
X
D7
DATA
P
A(S)
DATA[6...1]
t
BUF
t
R
P
S
DATA
A(M)
D0
P
ACK
STOP BIT
P