EVAL-ADN2804EB AD [Analog Devices], EVAL-ADN2804EB Datasheet - Page 21

• Manufacturer Part Number: EVAL-ADN2804EB
• Description: 622 Mbps Clock and Data Recovery IC with Integrated Limiting Amplifier
• Manufacturer: AD [Analog Devices]

APPLICATIONS INFORMATION
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal
performance.
Power Supply Connections and Ground Planes
Use of one low impedance ground plane is recommended. The
VEE pins should be soldered directly to the ground plane to
reduce series inductance. If the ground plane is an internal
plane and connections to the ground plane are made through
vias, multiple vias can be used in parallel to reduce the series
inductance, especially on Pin 23, which is the ground return for
the output buffers. The exposed pad should be connected to the
GND plane using plugged vias so that solder does not leak
through the vias during reflow.
Use of a 22 μF electrolytic capacitor between VCC and VEE is
recommended at the location where the 3.3 V supply enters the
PCB. When using 0.1 μF and 1 nF ceramic chip capacitors, they
should be placed between ADN2804 supply pins VCC and VEE,
as close as possible to the ADN2804 VCC pins.
VCC
0.1µF
TIA
+
22µF
0.1µF
1nF
50Ω
50Ω
1.6µF
1.6µF
Figure 24. Typical ADN2804 Applications Circuit
0.1µF
SLICEN
SLICEP
TEST1
VREF
VCC
VCC
VEE
NIN
PIN
1nF
0.1µF
R
TH
1
2
3
4
5
6
7
8
Rev. 0 | Page 21 of 24
EXPOSED PAD
1nF
TIED OFF TO
VEE PLANE
WITH VIAS
50Ω TRANSMISSION LINES
0.47µF ±20%
>300MΩ INSULATION RESISTANCE
If connections to the supply and ground are made through
vias, the use of multiple vias in parallel helps to reduce series
inductance, especially on Pin 24, which supplies power to the
high speed CLKOUTP/CLKOUTN and DATAOUTP/
DATAOUTN output buffers. Refer to Figure 24 for the
recommended connections.
By placing the power supply and GND planes adjacent to each
other and using close spacing between the planes, excellent high
frequency decoupling can be realized. The capacitance is given
by
where:
ε
A is the area of the overlap of power and GND planes (cm
d is the separation between planes (mm).
For FR-4, ε
C
r
PLANE
is the dielectric constant of the PCB material.
24
23
22
21
20
19
18
17
µC
C
VCC
VEE
SDA
SCK
SADDR5
VCC
VEE
LOS
~ 15.5A (pF)
PLANE
1nF
1nF
r
= 4.4 and d = 0.25 mm; therefore,
=
0.88ε
0.1µF
0.1µF
I
I
2
2
C CONTROLLER
C CONTROLLER
DATAOUTP
DATAOUTN
CLKOUTP
CLKOUTN
r
A
/
VCC
VCC
d
( )
pF
µC
ADN2804
2
).