EVAL-ADN2804EB AD [Analog Devices], EVAL-ADN2804EB Datasheet - Page 20

• Manufacturer Part Number: EVAL-ADN2804EB
• Description: 622 Mbps Clock and Data Recovery IC with Integrated Limiting Amplifier
• Manufacturer: AD [Analog Devices]

ADN2804
Using the Reference Clock to Measure Data Frequency
The user can also provide a reference clock to measure the
recovered data frequency. In this case, the user provides a
reference clock, and the ADN2804 compares the frequency of
the incoming data to the incoming reference clock and returns a
ratio of the two frequencies to within 0.01% (100 ppm) accuracy.
The accuracy error of the reference clock is added to the accuracy
of the ADN2804 data rate measurement. For example, if a 100 ppm
accuracy reference clock is used, the total accuracy of the measure-
ment is within 200 ppm.
The reference clock can range from 10 MHz to 160 MHz.
By default, the ADN2804 expects a reference clock between
10 MHz and 20 MHz. If the reference clock is between 20 MHz
and 40 MHz, 40 MHz and 80 MHz, or 80 MHz and 160 MHz,
the user must configure the ADN2804 for the correct reference
frequency range by setting two bits of the CTRLA register,
CTRLA[7, 6]. Using the reference clock to determine the frequency
of the incoming data does not affect the manner in which the
part locks onto data. In this mode, the reference clock is used
only to determine the frequency of the data.
Prior to reading back the data rate using the reference clock, the
CTRLA[7, 6] bits must be set to the appropriate frequency
range with respect to the reference clock being used. A fine data
rate readback is then executed as follows:
1. Write a 1 to CTRLA[1]. This enables the fine data rate
2. Reset MISC[2] by writing a 1 followed by a 0 to CTRLB[3].
Table 12.
D22
measurement capability of the ADN2804. This bit is level
sensitive and can perform subsequent frequency measurements
without being reset.
This initiates a new data rate measurement.
D21 ... D17
FREQ2[6:0]
D16
D15
Rev. 0 | Page 20 of 24
D14 ... D9
FREQ1[7:0]
3. Read back MISC[2]. If it is 0, the measurement is not
4. Read back the data rate from FREQ2[6:0], FREQ1[7:0], and
The data rate can be determined by
where:
FREQ[22:0] is the reading from FREQ2[6:0] (MSB byte,
FREQ1[7:0], and FREQ0[7:0] (LSB byte).
f
f
SEL_RATE is the setting from CTRLA[7, 6].
For example, if the reference clock frequency is 32 MHz,
SEL_RATE = 1, because the reference frequency falls into the
20 MHz to 40 MHz range, setting CTRLA[7, 6] to [01],.
Assume for this example that the input data rate is 622.08 Mb/s
(OC12). After following Step 1 through Step 4, the value that is
read back on FREQ[22:0] = 0x9B851, which is equal to 637 × 10
Plugging this value into the equation yields
If subsequent frequency measurements are required, CTRLA[1]
should remain set to 1. It does not need to be reset. The
measurement process is reset by writing a 1 followed by a 0 to
CTRLB[3]. This initiates a new data rate measurement. Follow
Step 2 through Step 4 to read back the new data rate.
Note that a data rate readback is valid only if LOL is low. If LOL
is high, the data rate readback is invalid.
DATARATE
REFCLK
complete. If it is 1, the measurement is complete and the
data rate can be read back on FREQ[22:0]. The time for a
data rate measurement is typically 80 ms.
FREQ0[7:0].
637e3 × 32e6/2
f
is the REFCLK frequency (MHz).
DATARATE
is the data rate (Mbps).
D8
=
(
FREQ
(14 + 1)
[
= 622.08 Mbps
D7
22
0 .
]
×
f
REFCLK
D6 ... D1
FREQ0[7:0]
)
2 /
(
14
+
SEL
_
RATE
)
D0
3
.