EVAL-ADN2804EB AD [Analog Devices], EVAL-ADN2804EB Datasheet

EVAL-ADN2804EB

Manufacturer Part Number

EVAL-ADN2804EB

Description

622 Mbps Clock and Data Recovery IC with Integrated Limiting Amplifier

Manufacturer

AD [Analog Devices]

Datasheet

1.EVAL-ADN2804EB.pdf (24 pages)

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FEATURES

Exceeds SONET requirements for jitter transfer/

Quantizer sensitivity: 3.3 mV typical

Adjustable slice level: ±95 mV

Patented clock recovery architecture

Loss-of-signal (LOS) detect range: 2.6 mV to 18.4 mV

Independent slice level adjust and LOS detector

No reference clock required

Loss-of-lock indicator

Single-supply operation: 3.3 V

Low power: 423 mW typical

5 mm × 5 mm, 32-lead LFCSP, Pb free

APPLICATIONS

BPON ONT

SONET OC-12

WDM transponders

Regenerators/repeaters

Test equipment

Broadband cross-connects and routers

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

C® interface to access optional features

generation/tolerance

SLICEP/SLICEN

VREF

NIN

THRADJ

QUANTIZER

FUNCTIONAL BLOCK DIAGRAM

DETECT

LOS

REFCLKP/REFCLKN

LOS

(OPTIONAL)

DATAOUTP/

DATAOUTN

RE-TIMING

SHIFTER

PHASE

DATA

622 Mbps Clock and Data Recovery IC

Figure 1.

LOL

FREQUENCY

DETECT

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

with Integrated Limiting Amplifier

GENERAL DESCRIPTION

The ADN2804 provides the receiver functions of quantization,

signal level detect, clock and data recovery, and data retiming

for 622 Mbps NRZ data. The ADN2804 automatically locks to

622 Mbps data without the need for an external reference clock

or programming. In the absence of input data, the output clock

drifts no more than ±5%. All SONET jitter requirements are

met, including jitter transfer, jitter generation, and jitter

tolerance. All specifications are quoted for −40°C to +85°C

ambient temperature, unless otherwise noted.

This device, together with a PIN diode and a TIA preamplifier,

can implement a highly integrated, low cost, low power fiber

optic receiver.

The receiver’s front-end loss-of-signal (LOS) detector circuit

indicates when the input signal level falls below a user-adjustable

threshold. The LOS detect circuit has hysteresis to prevent chatter

at the output.

The ADN2804 is available in a compact 5 mm × 5 mm,

32-lead LFCSP.

PHASE

CLKOUTP/

CLKOUTN

CF1

FILTER

LOOP

ADN2804

CF2

VCC

VCO

VEE

ADN2804

www.analog.com

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