EVAL-ADN2804EB AD [Analog Devices], EVAL-ADN2804EB Datasheet - Page 18

• Manufacturer Part Number: EVAL-ADN2804EB
• Description: 622 Mbps Clock and Data Recovery IC with Integrated Limiting Amplifier
• Manufacturer: AD [Analog Devices]

ADN2804
To control the device on the bus, the following protocol must be
followed. First, the master initiates a data transfer by establish-
ing a start condition, defined by a high-to-low transition on
SDA while SCK remains high. This indicates that an address/
data stream follows. All peripherals respond to the start condition
and shift the next eight bits (the 7-bit address and the R/W bit).
The bits are transferred from MSB to LSB. The peripheral that
recognizes the transmitted address responds by pulling the data
line low during the ninth clock pulse. This is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition is
where the device monitors the SDA and SCK lines, waiting for
the start condition and correct transmitted address. The R/W
bit determines the direction of the data. Logic 0 on the LSB of
the first byte means that the master writes information to the
peripheral. Logic 1 on the LSB of the first byte means that the
master reads information from the peripheral.
The ADN2804 acts as a standard slave device on the bus. The data
on the SDA pin is eight bits long, supporting the 7-bit addresses
plus the R/W bit. The ADN2804 has eight subaddresses to enable
the user-accessible internal registers (see Table 6 through Table
10). It, therefore, interprets the first byte as the device address
and the second byte as the starting subaddress. Auto-increment
mode is supported, allowing data to be read from or written to
the starting subaddress and each subsequent address without
manually addressing the subsequent subaddress. A data transfer
is always terminated by a stop condition. The user can also
access any unique subaddress register on a one-by-one basis
without updating all registers.
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Stop and start conditions can be detected at any stage of the
data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCK high period, the
user should issue one start condition, one stop condition, or a
single stop condition followed by a single start condition. If an
invalid subaddress is issued by the user, the ADN2804 does not
issue an acknowledge and returns to the idle condition. If the
user exceeds the highest subaddress while reading back in auto-
increment mode, then the highest subaddress register contents
continue to be output until the master device issues a no acknow-
ledge. This indicates the end of a read. In a no-acknowledge
condition, the SDATA line is not pulled low on the ninth pulse.
See Figure 8 and Figure 9 for sample write and read data transfers
and Figure 10 for a more detailed timing diagram.
Additional Features Available via the I
LOS Configuration
The LOS detector output, Pin 22, can be configured to be either
active high or active low. If CTRLC[2] is set to Logic 0 (default),
the LOS pin is active high when a loss-of-signal condition is
detected. Writing a 1 to CTRLC[2] configures the LOS pin to be
active low when a loss-of-signal condition is detected.
System Reset
A frequency acquisition can be initiated by writing a 1 followed
by a 0 to the I
frequency acquisition while keeping the ADN2804 in its
previously programmed operating mode, as set in Registers
CTRL[A], CTRL[B], and CTRL[C].
2
C Register Bit CTRLB[5]. This initiates a new
2
C Interface