M37754 Mitsubishi, M37754 Datasheet - Page 73

• Manufacturer Part Number: M37754
• Description: SINGLE-CHIP 16BIT CMOS MICROCOMPUTER
• Manufacturer: Mitsubishi

Processor modes are explained bellow.
Fig. 86 External memory area for each mode
(1) Single-chip mode [00]
The microcomputer enters the single-chip mode by connecting the
CNVss pin to Vss and starting from reset. Ports P0 to P4, P10 and
P11 all function as normal I/O ports. Port P4
source
In this mode, enable signal E is output from pin E/RD. Signal E out-
put can be stopped by setting the signal output disable select bit (bit
4 of particular function select register 1) to “1”, and it is possible to
switch the output to “L” level. Table 8 shows the function of the signal
output disable select bit’s function.
(2) Memory expansion mode [01]
The microcomputer enters the memory expansion mode by setting
the processor mode bits to “01” after connecting the CNVss pin to
Vss and starting from reset.
Pin E/RD becomes the RD output pin. RD is an read signal, and read
is performed during it is “L” level. When the internal memory area is
read, the RD output can be fixed to “H” by setting the signal output
disable select bit to “1”.
Ports P0, P1 and P2 become the output pins of addresses A
and A
Port P10 becomes I/O pins of data D
function. When the BYTE pin’s level is “L”, those pins function as
data I/O pins at an even address. When the level is “H”, those pins
function as data I/O pins at even and odd addresses. However, if an
internal memory area is read, external data is not input
When the BYTE pin’s level is “H” and the multiplex bus select bit (bit
5 of chip select area register; Figure 88) is “1”, port P10 functions as
_ __
23
, and their I/O port function are lost.
1
___
16
by setting bit 7 of the processor mode register 0 to “1”.
FFFFFF
The shaded area is the external memory area.
2
16
16
to 19
to 9
80
Memory expansion
16
16
16
16
___
mode
ROM
RAM
SFR
_
___
0
Microprocessor
to D
mode
RAM
SFR
7
and loses its I/O port
_ ___
2
can output clock
M37754M8C-XXXGP, M37754M8C-XXXHP
0
_
to A
19
____
_____
____
follows during the bus cycle in which the external memory area cor-
responding to the chip select CS
That is, it functions as a multiplex bus during that bus cycle.
Port P11 has two functions depending on the level of the BYTE pin.
When the BYTE pin level is “L”, those pins function as data D
I/O pins at an odd address. The I/O port function is lost. However, if
an internal memory area is read, external data is not input. When the
BYTE pin level is “H”, port P11 functions as a programmable port
P11 similarly in the single-chip mode.
Ports P3
output pins respectively and lose their I/O port functions.
___
WR is a write signal which indicates a write when it is “L”.
BHE is a byte-high-enable signal which indicates that an odd ad-
dress is accessed when it is “L”.
Therefore, two bytes at even and odd addresses are accessed si-
multaneously when address A
ALE is an address-latch-enable signal. The latch is open while ALE
is “H”, so that the address signal passes through; the address is held
while ALE is “L”.
HLDA is a hold-acknowledge signal and is used to indicate to the
external that the microcomputer accepts HOLD input and enters
Hold state.
Ports P4
and their I/O port function are lost.
_____
HOLD is a hold-request signal. It is an input signal used to make the
microcomputer enter Hold state. HOLD input is accepted when the
state,
= “L”), RD, WR and BHE become floating then. These pins become
floating one cycle of
When terminating Hold state, these pins are terminated from floating
state one cycle of
RDY is a ready signal. When this signal goes “L”,
stop at “L”. RDY is used when a slow external memory is connected
and others.
Port P4
mode register 0 is “0” and becomes the clock
7 is “1”. The
even when
•Output pins of addresses LA
•Data input/output pins at even and odd addresses during “L” of RD
A
or WR.
BIU
M37754S4CGP, M37754S4CHP
0
___
to A
has fallen from “H” to “L” level while the bus is not used. In Hold
___ ___
CPU
2
7
0
0
, during “H” of RD or WR.
becomes a normal I/O port when bit 7 of the processor
, P3
and P4
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
____
stops at “L”. A
CPU
1
, P3
1
1
output is independent of RDY and does not stop
and
become HOLD and RDY input pins, respectively,
2
____
BIU
, and P3
BIU
MITSUBISHI MICROCOMPUTERS
___
later than HLDA signal becomes “H” level.
BIU
0
later than HLDA signal becomes “L” level.
to A
_____
stop owing to “L” input to the RDY pin.
3
0
___
0
___
become WR, BHE, ALE, and HLDA
to LA
19
is “L” and BHE is “L”.
4
, A
_____
_____
are accessed:
23
_____
7
, same as low-order addresses
, D
____
___
0
____
to D
____
_____
____
7
1
, D
output pin when bit
8
to D
CPU
15
____
and
(at BYTE
8
_____
to D
___
BIU
73
15