M37754 Mitsubishi, M37754 Datasheet - Page 69

• Manufacturer Part Number: M37754
• Description: SINGLE-CHIP 16BIT CMOS MICROCOMPUTER
• Manufacturer: Mitsubishi

STANDBY FUNCTION
The WIT and the STP instructions make the microcomputer standby
state.
Table 7 shows the relation between standby state and each block’s
operation.
The WIT/STP state is terminated by interrupt acceptance or reset.
Accordingly, it is necessary to prepare the state in which any inter-
rupt can be accepted before the WIT/STP instruction is executed.
WIT instruction
When the WIT instruction is executed with the internal clock stop
select bit at WIT (bit 2 of particular function select register 1; Figure
62) = “0”, the clock sources
ever, the oscillation circuit, the clock source
clocks Pf
though the CPU and bus interface unit stop operation, internal pe-
ripheral devices which use these divided clocks can operate even at
WIT state.
Otherwise, when the WIT instruction is executed with the internal
clock stop select bit at WIT = “1”, the oscillation circuit is not stopped,
however, the clock source
nal peripheral devices and the watchdog timer which use divided
clocks Pf
When internal peripheral devices are not used in WIT state, the lat-
ter state (internal clock stop select bit at WIT = “1”) is more effective
to reduce current consumption.
Make sure to set the internal clock stop select bit at WIT to “1” imme-
diately before the WIT instruction execution and clear the bit to “0”
immediately after the WIT state is terminated.
The WIT state is terminated when an interrupt request is accepted,
and the internal clock
can immediately be executed because oscillation circuit’s operation
is not stopped during WIT state.
Table 7 Relation between standby state and each block’s operation.
Notes 1 : When the clock external input select bit is “1”, the clock oscillation circuit stops. An external clock can be input.
BIU
Instruction
and
STP
WIT
2 : When the watchdog timer clock select bit is “1”, Wf
2
2
to Pf
to Pf
CPU
512
are stopped. Accordingly, in this case, all of the inter-
512
stop bit at WIT
, Wf
Internal clock
, Wf
32
32
“0”
“1”
—
operation is restarted. Interrupt processing
, and Wf
, Wf
1
, divided clocks, and the clock sources
BIU
512
512
and
are not stopped. Accordingly, al-
Oscillation
Operating
Operating
are stopped.
(Note 1)
(Note 1)
Stopped
circuit
CPU
are stopped at “L”, how-
1
, and the divided
Operating
Stopped
Stopped
M37754M8C-XXXGP, M37754M8C-XXXHP
(“L”)
(“L”)
32
and Wf
1
512
Pf
stop. The watchdog timer operates with Pf
Operating
Stopped
Stopped
2
(“H”)
(“H”)
to Pf
Operation at WIT/STP state
STP instruction
When the STP instruction is executed, the oscillation circuit is
stopped and the clock sources
thermore, “FFF
its clock source is forced to connect with Wf
timer clock select bit = “0”, or Pf
is cut off when the most significant bit of the watchdog timer be-
comes “0” or the microcomputer is reset, and the clock source is con-
nected with the input depending on the contents of the watchdog
timer frequency select register and the watchdog timer clock select
bit. In STP state, all of the internal peripheral devices and the watch-
dog timer which use divided clocks Pf
stopped.
The STP state is terminated by reset or interrupt request accep-
tance, and then oscillation is restarted. At the same time, supply of
the clock source
is restarted.
In that condition, when the STP return select bit (bit 7 of particular
function select register 0) is “0”, the clock sources
stop at “L” until the most significant bit of the watchdog timer
decremented with divided clock Pf
supply of the clock sources
after the oscillation restarts by reset. Accordingly, in this case, wait
for enough time to stabilize the oscillation before the reset input of
“H”.
Otherwise in that condition, when the STP return select bit is “1”,
supply of the clock sources
of the divided clock Pf
function makes it possible to immediately return from STP state
when the clock supply input to the X
Even though clocks are input from the external, make sure to clear
the STP return select bit to “0” if the external clock is unstable for a
short time when returning from STP state
512
M37754S4CGP, M37754S4CHP
Wf
Operating
(Note 2)
Stopped
Stopped
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2
(“H”)
(“H”)
, Wf
16
512
” is automatically set into the watchdog timer, and
1
and divided clocks Pf
16
MITSUBISHI MICROCOMPUTERS
’s “H” to “L” after the oscillation restarts. This
Stopped
Stopped
Stopped
BIU
(“L”)
(“L”)
(“L”)
BIU
BIU
,
32
32
CPU
or Pf
and
and
when the bit = “1”. This connection
1
32
,
IN
or Wf
2
512
BIU
from the external is stabilized.
to Pf
CPU
CPU
Internal peripheral devices
(Watchdog timer operating)
.
(Watchdog timer stopped)
(Watchdog timer stopped)
using Pf
2
and
32
to Pf
512
is restarted at the timing
Operation disabled
Operation disabled
is restarted immediately
Operation enabled
becomes “0”. However,
32
, Wf
when the watchdog
512
CPU
2
Wf
32
, Wf
to Pf
, and Wf
are at “L”. Fur-
512
BIU
32
512
and
and Wf
, Wf
512
32
CPU
are
512
,
69