M37754 Mitsubishi, M37754 Datasheet - Page 13
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M37754
Manufacturer Part Number
M37754
Description
SINGLE-CHIP 16BIT CMOS MICROCOMPUTER
Manufacturer
Mitsubishi
Datasheet
1.M37754.pdf
(114 pages)
Available stocks
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Part Number
Manufacturer
Quantity
Price
Part Number:
M37754S4CGP
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Instruction code read, data read, and data write are described below.
Instruction code read will be described first.
The CPU obtains instruction codes from the instruction queue buffer
and executes them. The CPU notifies the bus interface unit that CPU
is requesting an instruction code during an instruction code request
cycle. If the requested instruction code is not yet stored in the instruc-
tion queue buffer, the bus interface unit halts the CPU until it can
store more instructions than requested in the instruction queue
buffer.
Even if there is no instruction code request from the CPU, the bus
interface unit reads instruction codes from memory and stores them
in the instruction queue buffer when the instruction queue buffer is
empty or when only one instruction code is stored and the bus is idle
on the next cycle.
This is referred to as instruction pre-fetching.
Normally, when reading an instruction code from memory, if the ac-
cessed address is even, the next odd address is read together with
the instruction code and stored in the instruction queue buffer.
However, in memory expansion mode or microprocessor mode, if the
bus width select input (BYTE) is “H” and external data bus width is 8
bits, and if the address to be read is in external memory area or is
odd, only one byte is read and stored in the instruction queue buffer.
Data read and write are described below.
The CPU notifies the bus interface unit when performing data read
or write. At this time, the bus interface unit halts the CPU if the bus
interface unit is already using the bus or if there is a request with
higher priority. When data read or write is enabled, the bus interface
unit performs data read or write.
During data read, the CPU waits until the entire data is stored in the
data buffer. The bus interface unit sends the address sent from the
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