M37754 Mitsubishi, M37754 Datasheet - Page 61

• Manufacturer Part Number: M37754
• Description: SINGLE-CHIP 16BIT CMOS MICROCOMPUTER
• Manufacturer: Mitsubishi

WATCHDOG TIMER
The watchdog timer is used to detect unexpected execution se-
quence caused by software runaway and others. Figure 74 shows
the block diagram of the watchdog timer.
The watchdog timer consists of a 12-bit binary counter.
The watchdog timer counts clock Wf
viding the peripheral devices’ clock Pf
which is obtained by doing it by 256. The watchdog timer frequency
select register shown in Figure 75 selects which clock is counted.
Wf
selected when they are “1”. They are cleared to “0” after reset.
The watchdog timer clock select bit (bit 3 of particular function select
register 1; Figure 62) selects use of clock Wf
as the clock source of watchdog timer. When selecting Wf
the clock source of watchdog timer (Wf
Hold state. When selecting Pf
timer (Pf
sumption can be reduced. It is because the Wf
cuit stops.
FFF
______
RESET pin, STP instruction is executed, data is written to the watch-
dog timer, or the most significant bit of the watchdog timer becomes
“0”.
After FFF
counts the clock source by 2048 counts, the most significant bit of
watchdog timer becomes “0”, the watchdog timer interrupt request
bit is set to “1”, and FFF
Normally, a program is written so that data is written in the watchdog
timer before the most significant bit of the watchdog timer becomes
“0”. If this routine is not executed owing to unexpected program ex-
ecution and others, the most significant bit of the watchdog timer
becomes “0” and an interrupt is generated.
The microcomputer can be reset by writing “1” to bit 3 (software re-
set bit) of processor mode register 0 in the interrupt routine, de-
scribed in Figure 16 in the interrupt section, and generating a reset
pulse.
The watchdog timer stops its function when the RESET pin voltage
is raised to double the Vcc voltage.
The watchdog timer can also be used to return from when the clock
is stopped by the STP instruction. Refer to the section on the clock
generating circuit for more details.
The watchdog timer also becomes Hold state during Hold state and
the clock input to it is stopped.
512
16
/Pf
is set in the watchdog timer when “L” or 2Vcc is applied to the
512
512
16
/Pf
is selected when its contents are “0”, and Wf
is set in the watchdog timer, when the watchdog timer
32
) is active during Hold state, however, current con-
16
is set again in the watchdog timer.
512
/Pf
32
32
, the clock source of watchdog
/Pf
2
512
by 16; or clock Wf
32
/Wf
, which is obtained by di-
32
512
512
) is not active during
______
/Wf
/Wf
32
32
M37754M8C-XXXGP, M37754M8C-XXXHP
or Pf
division cir-
512
32/
512
512
Pf
/Pf
/Wf
/Pf
32
512
32
32
is
,
,
Fig. 74 Watchdog timer block diagram
Fig. 75 Watchdog timer frequency select register bit configuration
Hold request
Clock source for peripheral
devices
M37754S4CGP, M37754S4CHP
7
STP instruction
6
6
Watchdog timer frequency select register
RESET
Pf
1/8
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2
5
5
Pf
Write to watchdog timer
16
4
4
1/2
Watchdog timer clock select bit
3
3
MITSUBISHI MICROCOMPUTERS
1/16
1/2
detection
2
2
2Vcc
S
R
1
1
0
1/8
Wf
Q
1/16
Pf
0
0
32
32
Pf
Hold request
512
Wf
Watchdog timer frequency
select register
0 : W f
1 : W f
This bit must be fixed to “0.”
512
512
32
STP return select bit
or Pf
or Pf
32
Wachdog timer
Address 60
512
selected
selected
Set FFF
Address
Pf
61
16
16
16
16
61