T89C51CC02 Atmel, T89C51CC02 Datasheet - Page 48

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T89C51CC02

Manufacturer Part Number
T89C51CC02
Description
8-Bit MCU
Manufacturer
Atmel
Datasheet

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T89C51CC02
11.5. REGISTERS
SCON (S:98h)
Serial Control Register
Reset Value = 0000 0000b
Bit addressable
48
Bit Number Bit Mnemonic
FE/SM0
7
7
6
5
4
3
2
1
0
SM1
SM0
SM1
SM2
REN
TB8
RB8
FE
RI
TI
6
Framing Error bit (SMOD0=1)
Serial port Mode bit 0 (SMOD0=0)
Serial port Mode bit 1
Serial port Mode 2 bit / Multiprocessor Communication Enable bit
Reception Enable bit
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3
Receiver Bit 8 / Ninth bit received in modes 2 and 3
Transmit Interrupt flag
Receive Interrupt flag
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
Refer to SM1 for serial port mode selection.
SM0
0
0
1
1
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3.
Clear to disable serial reception.
Set to enable serial reception.
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other
modes.
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 27. and Figure 28. in the other modes.
SM2
5
Figure 29. SCON Register
Preliminary
SM1
0
1
0
1
REN
4
Shift RegisterF
8-bit UARTVariable
9-bit UARTF
9-bit UARTVariable
ModeBaud Rate
TB8
3
Description
XTAL
XTAL
/64 or F
RB8
/12
2
XTAL
/32
TI
Rev.A - May 17, 2001
1
RI
0

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