T89C51CC02 Atmel, T89C51CC02 Datasheet - Page 20

• Manufacturer Part Number: T89C51CC02
• Description: 8-Bit MCU
• Manufacturer: Atmel

T89C51CC02
7.3. Overview of FM0 operations
The CPU interfaces to the flash memory through the FCON register and AUXR1 register.
These registers are used to:
7.3.1. Mapping of the memory space
By default, the user space is accessed by MOVC instruction for read only. The column latches space is made
accessible by setting the FPS bit in FCON register. Writing is possible from 0000h to 3FFFh, address bits 6 to 0
are used to select an address within a page while bits 14 to 7 are used to select the programming address of the page.
Setting this bit takes precedence on the EXTRAM bit in AUXR register.
The other memory spaces (user, extra row, hardware security) are made accessible in the code segment by
programming bits FMOD0 and FMOD1 in FCON register in accordance with Table 13. A MOVC instruction is
then used for reading these spaces.
7.3.2. Launching programming
FPL3:0 bits in FCON register are used to secure the launch of programming. A specific sequence must be written
in these bits to unlock the write protection and to launch the programming. This sequence is 5 followed by A.
Table 14 summarizes the memory spaces to program according to FMOD1:0 bits.
20
Map the memory spaces in the adressable space
Launch the programming of the memory spaces
Get the status of the flash memory (busy/not busy)
Select the flash memory FM0/FM1.
Security Space
Extra Row
Reserved
User
FPL3:0
A
A
A
A
5
5
5
5
FMOD1
0
0
1
1
FPS
Write to FCON
X
X
X
X
X
X
X
X
Table 13. .FM0 blocks select bits
Table 14. Programming spaces
FMOD0
0
1
0
1
Preliminary
FMOD1
0
0
0
0
1
1
1
1
User (0000h-3FFFh)
Extra Row(FF80h-FFFFh)
Hardware Security (0000h)
reserved
FM0 Adressable space
FMOD0
0
0
1
1
0
0
1
1
No action
Write the column latches in user space
No action
Write the column latches in extra row space
No action
Write the fuse bits space
No action
No action
Operation
Rev.A - May 17, 2001