T89C51CC02 Atmel, T89C51CC02 Datasheet - Page 30

no-image

T89C51CC02

Manufacturer Part Number
T89C51CC02
Description
8-Bit MCU
Manufacturer
Atmel
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
T89C51CC02CA-RATIM
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
T89C51CC02CA-SISIM
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
T89C51CC02UA-RATIM
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
T89C51CC02UA-SISIM
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
T89C51CC02UA-SITIM
Manufacturer:
Atmel
Quantity:
10 000
T89C51CC02
8.3. Dual Data Pointer
8.3.1. Description
The T89C51CC02 implements a second data pointer for speeding up code execution and reducing code size in
case of intensive usage of external memory accesses.
DPTR0 and DPTR1 are seen by the CPU as DPTR and are accessed using the SFR addresses 83h and 84h that
are the DPH and DPL addresses. The DPS bit in AUXR1 register (see Figure 17) is used to select whether DPTR
is the data pointer 0 or the data pointer 1 (see Figure 15).
8.3.2. Application
Software can take advantage of the additional data pointers to both increase speed and reduce code size, for
example, block operations (copy, compare, search …) are well served by using one data pointer as a “source”
pointer and the other one as a “destination” pointer.
Hereafter is an example of block move implementation using the two pointers and coded in assembler. Latest C
compiler take also advantage of this feature by providing enhanced algorithm libraries.
The INC instruction is a short (2 bytes) and fast (6 CPU clocks) way to manipulate the DPS bit in the AUXR1
register. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply
toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper
sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0'
or '1' on entry.
; ASCII block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; Ends when encountering NULL character
; Note: DPS exits opposite of entry state unless an extra INC AUXR1 is added
AUXR1
move:
mv_loop:
end_move:
30
EQU
mov
inc
mov
inc
movx
inc
inc
movx
inc
jnz
0A2h
DPTR,#SOURCE
AUXR1
DPTR,#DEST
AUXR1
A,@DPTR
DPTR
AUXR1
@DPTR,A
DPTR
mv_loop
DPTR1
Figure 15. Dual Data Pointer Implementation
DPTR0
Preliminary
DPH0
DPH1
DPL0
DPL1
; address of SOURCE
; switch data pointers
; address of DEST
; switch data pointers
; get a byte from SOURCE
; increment SOURCE address
; switch data pointers
; write the byte to DEST
; increment DEST address
; check for NULL terminator
DPS
0
1
0
1
AUXR1.0
DPL
DPH
DPTR
Rev.A - May 17, 2001

Related parts for T89C51CC02