SB82371 Intel Corporation, SB82371 Datasheet - Page 76

• Manufacturer Part Number: SB82371
• Description: 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR
• Manufacturer: Intel Corporation

82371FB (PIIX) AND 82371SB (PIIX3)
2.5.5.
The NMI logic incorporates two different 8-bit registers. The CPU reads the NMISC Register to determine the
NMI source (bits set to a 1). After the NMI interrupt routine processes the interrupt, software clears the NMI
status bits by setting the corresponding enable/disable bit to a 1. The NMI Enable and Real-Time Clock
Register can mask the NMI signal and disable/enable all NMI sources.
To ensure that all NMI requests are serviced, the NMI service routine software flow should be as follows:
1. NMI is detected by the processor on the rising edge of the NMI input.
2. The processor will read the status stored in port 061h to determine what sources caused the NMI. The
3. The processor must then disable all NMIs by setting bit 7 of port 070H to a 1 and then enable all NMIs by
2.5.5.1.
I/O Address:
Default Value:
Attribute:
This register reports the status of different system components, control the output of the speaker counter
(Counter 2), and gate the counter output that drives the SPKR signal.
76
1
0
Bit
7
6
5
Bit
processor may then set to 0 the register bits controlling the sources that it has determined to be active.
Between the time the processor reads the NMI sources and sets them to a 0, an NMI may have been
generated by another source. The level of NMI will then remain active. This new NMI source will not be
recognized by the processor because there was no edge on NMI.
setting bit 7 of port 070H to a 0. This will cause the NMI output to transition low then high if there are any
pending NMI sources. The CPU’s NMI input logic will then register a new NMI.
System Reset (SRST). This bit is used in conjunction with bit 2 in this register to initiate a hard
reset. When SRST =1, the PIIX/PIIX3 initiates a hard reset to the CPU when bit 2 in this register
transitions from 0 to 1. When SRST=0, the PIIX/PIIX3 initiates a soft reset when bit 2 in this
register transitions from 0 to 1.
Reserved
NMI REGISTERS
SERR# NMI Source Status—RO. Bit 7 is set if a system board agent (PCI devices or main
memory) detects a system board error and pulses the PCI SERR# line. This interrupt source is
enabled by setting bit 2 to 0. To reset the interrupt, set bit 2 to 0 and then set it to 1. When
writing to port 061h, bit 7 must be 0.
IOCHK# NMI Source Status—RO. Bit 6 is set if an expansion board asserts IOCHK# on the
ISA Bus. This interrupt source is enabled by setting bit 3 to 0. To reset the interrupt, set bit 3 to
0 and then set it to 1. When writing to port 061h, bit 6 must be a 0.
Timer Counter 2 OUT Status—RO. The Counter 2 OUT signal state is reflected in bit 5. The
value on this bit following a read is the current state of the Counter 2 OUT signal. Counter 2
must be programmed following a CPURST for this bit to have a determinate value. When
writing to port 061h, bit 5 must be a 0.
NMISC—NMI Status And Control Register
061h
00h
Read/Write
Description
Description