SB82371 Intel Corporation, SB82371 Datasheet - Page 16

• Manufacturer Part Number: SB82371
• Description: 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR
• Manufacturer: Intel Corporation

82371FB (PIIX) AND 82371SB (PIIX3)
1.7.
1.8.
16
IRQ[15,14,
11:9, 7:3,1]
IRQ8#
IRQ12/M
PIRQ[D:A]#
INTR
NMI
SMI#
STPCLK#
EXTSMI#
Signal Name
Signal Name
Interrupt Controller Signals
System Power Management (SMM) Signals
od
od
I
Type
I
I
I
I
I/O For
PIRQD#
(PIIX3
only)
od
od
Type
SYSTEM MANAGEMENT INTERRUPT: SMI# is an active low
synchronous output that is asserted by the PIIX/PIIX3 in response to one
of many enabled hardware or software events.
STOP CLOCK: STPCLK# is an active low synchronous output that is
asserted by the PIIX/PIIX3 in response to one of many hardware or
software events. STPCLK# connects directly to the CPU and is
synchronous to PCICLK.
EXTERNAL SYSTEM MANAGEMENT INTERRUPT: EXTSMI# is a
falling edge triggered input to the PIIX/PIIX3 indicating that an external
device is requesting the system to enter SMM mode. This signal contains
a weak internal pullup.
INTERRUPT REQUEST: The IRQ signals provide both system board
components and ISA Bus I/O devices with a mechanism for
asynchronously interrupting the CPU. The assertion mode of these
inputs depends on the programming of the two ELCR registers. The
IRQ14 signal must be used by the Bus Master IDE interface function
to signal interrupts on the primary IDE channel.
INTERRUPT REQUEST EIGHT SIGNAL: IRQ8# is always an active
low edge triggered interrupt input (i.e., this interrupt can not be
modified by software). Upon PCIRST#, IRQ8# is placed in active low
edge sensitive mode.
INTERRUPT REQUEST/MOUSE INTERRUPT: In addition to
providing the standard interrupt function (see IRQ[15,14,11:9,7:3,1]
signal description), this pin can be programmed (via X-Bus Chip
Select Register) to provide a mouse interrupt function.
PROGRAMMABLE INTERRUPT REQUEST: The PIRQx# signals
can be shared with interrupts IRQ[15,14,12:9,7:3] as described in the
Interrupt Steering section. Each PIRQx# line has a separate Route
Control Register. These signals require external pull-up resisters.
For the PIIX3, the USB interrupt is output on PIRQD#.
CPU INTERRUPT: INTR is driven by the PIIX/PIIX3 to signal the CPU
that an interrupt request is pending and needs to be serviced. The
interrupt controller must be programmed following PCIRST# to ensure
that INTR is at a known state.
NON-MASKABLE INTERRUPT: NMI is used to force a non-maskable
interrupt to the CPU. The PIIX/PIIX3 generates an NMI when either
SERR# or IOCHK# is asserted, depending on how the NMI Status
and Control Register is programmed.
Description
Description