SB82371 Intel Corporation, SB82371 Datasheet - Page 54

• Manufacturer Part Number: SB82371
• Description: 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR
• Manufacturer: Intel Corporation

82371FB (PIIX) AND 82371SB (PIIX3)
2.4.2.
Address Offset:
Default Value:
Attribute:
The DID Register contains the device identification number. This register, along with the VID Register, define
the PIIX. Writes to this register have no effect.
2.4.3.
Address Offset:
Default Value:
Attribute:
This register controls access to the I/O space registers.
54
15:0
15:10
9
8:5
4
3
2
1
0
Bit
Bit
DID DEVICE IDENTIFICATION REGISTER (Function 2) (PIIX3)
PCICMD COMMAND REGISTER (Function 2) (PIIX3)
Device Identification Number. This is a 16-bit value assigned to the PIIX3.
Reserved. Read 0.
Fast Back to Back Enable (FBE). (Not Implemented) This bit is hardwired to 0.
Reserved. Read as 0.
Memory Write and Invalidate Enable (MWI). (Not Implemented) This bit is hardwired to
0.
Special Cycle Enable (SCE). (Not Implemented) This bit is hardwired to 0.
Bus Master Enable (BME). This bit controls the PIIX3’s ability to act as a master on the
PCI bus for the host controller transfers. A value of 0 disables the device from generating
PCI accesses. A value of 1 allows the device to behave as a USB host controller bus
master. This bit must be set to 1 before serial bus transactions can start.
Memory Space Enable (MSE). (Not Implemented) This bit is hardwired to 0.
I/O Space Enable (IOSE). 1=Enable. 0=Disable. This bit controls the access to the I/O
space registers. If this bit is set, access to the host controller IO registers is enabled. The
base register for the I/O registers must be programmed before this bit is set.
02 03h
7020h
Read Only
04 05h
00h
Read/Write
Description
Description