SB82371 Intel Corporation, SB82371 Datasheet - Page 12

• Manufacturer Part Number: SB82371
• Description: 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR
• Manufacturer: Intel Corporation

82371FB (PIIX) AND 82371SB (PIIX3)
Signals Buffered from LA[23:17]
These signals are buffered from the LA[23:17] lines by an ALS244 tri-state buffer. The output enable of this
buffer is tied asserted. These signals are set up with respect to the IDE command strobes (DIOR# and IOW#)
and are valid throughout I/O transactions targeting the ATA register block(s).
12
IORDY
SOE#
SDIR
Signal Name
LA23/
CS1S
LA22/
CS3S
LA21/
CS1P
LA20/
CS3P
LA[19:17]
DA[2:0]
Signal Name
I/O
I/O
I/O
I/O
I/O
Type
I
O
O
Type
CHIP SELECT: CS1S is for the ATA command register block and
corresponds to the inverted CS1FX# on the secondary IDE connector.
CS1S is inverted externally (see PCI Local Bus IDE section).
CHIP SELECT: CS3S is for the ATA control register block and
corresponds to the inverted CS3FX# on the secondary IDE connector.
CS3S is inverted externally (see PCI Local Bus IDE section).
CHIP SELECT: CS1P is for the ATA command register block and
corresponds to the inverted CS1FX# on the primary IDE connector. CS1P
is inverted externally (see PCI Local Bus IDE section).
CHIP SELECT: CS3P is for the ATA control register block and
corresponds to the inverted CS3FX# on the primary IDE connector. CS3P
is inverted externally (see PCI Local Bus IDE section).
DISK ADDRESS: DA[2:0] are used to indicate which byte in either the
ATA command block or control block is being addressed.
IO CHANNEL READY: This input signal is directly driven by the
corresponding signal on up to two IDE connectors (primary and
secondary).
SYSTEM ADDRESS TRANSCEIVER OUTPUT ENABLE: This signal
controls the output enables of the ’245 transceivers that interface the
DD[15:0] signals to the SA[19:8], SBHE#, PCS# and APICCS# (PIIX3
only) signals.
SYSTEM ADDRESS TRANSCEIVER DIRECTION: This signal controls
the direction of the ’245 transceivers that interface the DD[15:0] signals
to the SA[19:8], SBHE#, PCIS, and APICCS# (PIIX3 only), signals.
Default condition is high (transmit). When an ISA Bus master is granted
use of the bus, the transceivers are turned around to drive the ISA
address [19:8] on DD[15:3]. The address can then be latched by the
PIIX/PIIX3. In this case, the SDIR signal is low (receive). The SOE# and
SDIR signals taken together as a group can assume one of three states:
SOE#
0
1
0
SDIR
1
1
0
State
PCI to ISA transaction
PCI to IDE
ISA Bus master
Description
Description