SB82371 Intel Corporation, SB82371 Datasheet - Page 52

• Manufacturer Part Number: SB82371
• Description: 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR
• Manufacturer: Intel Corporation

82371FB (PIIX) AND 82371SB (PIIX3)
2.3.11.
Address Offset:
Default Value:
Attribute:
This register controls the PIIX3’s IDE interface and selects the timing characteristics for the slave drives on
each IDE channel. This allows for programming of independent operating modes for each IDE agent. This
register has no affect unless the SITRE bit is enabled in the IDETIM Register.
52
4
3
2
1
0
7:6
Bit
Bit
SIDETIM—SLAVE IDE TIMING REGISTER (Function 1) (PIIX3 Only)
Fast Timing Bank Drive Select 1 (TIME1). When TIME1=0, accesses to the data port of
the enabled I/O address range use the 16-bit compatible timing PCI local bus path.
When TIME1=1 and the currently selected drive (via a copy of bit 4 of 1x6h) is Drive 1,
accesses to the data port of the enabled I/O address range use the fast timing bank PCI local
bus IDE path. Accesses to the data port use fast timing only if bit 7 of this register (DTE1) is
zero. Accesses to all non-data ports of the enabled I/O address range use the 8-bit
compatible timing PCI local bus path.
DMA Timing Enable Only (DTE0). When DTE0=1, fast timing mode is enabled for DMA
data transfers for drive 0. Note that PIO transfers to the IDE data port still run in compatible
timing.
Prefetch and Posting Enable (PPE0). 1=Enable; 0=Disable. When enabled, prefetch and
posting to the IDE data port is enabled for drive 0.
IORDY Sample Point Enable Drive Select 0 (IE0). When IE0=0, IORDY sampling is
disabled for Drive 0. The internal IORDY signal is forced asserted guaranteeing that IORDY
is sampled asserted at the first sample point as specified by the ISP field in this register.
When IE0=1 and the currently selected drive (via a copy of bit 4 of 1x6h) is Drive 0, all
accesses to the enabled I/O address range sample IORDY. The IORDY sample point is
specified by the ISP field in this register.
Fast Timing Bank Drive Select 0 (TIME0). When TIME0=0, accesses to the data port of
the enabled I/O address range uses the 16-bit compatible timing PCI local bus path.
When TIME0=1 and the currently selected drive (via a copy of bit 4 of 1x6h) is Drive 0,
accesses to the data port of the enabled I/O address range use the fast timing bank PCI local
bus IDE path. Accesses to the data port use fast timing only if bit 3 of this register (DTE0) is
0. Accesses to all non-data ports of the enabled I/O address range use the 8-bit compatible
timing PCI local bus path.
Secondary Drive 1 IORDY Sample Point (SISP1). This field selects the number of clocks
between DIOx# assertion and the first IORDY sample point for the slave drive on the
secondary channel.
Bits[7:6]
00
01
10
11
44h
00h
Read / Write Only
Number Of Clocks
5
4
3
2
Description
Description