XC68HC08KH12 Motorola, XC68HC08KH12 Datasheet - Page 209

• Manufacturer Part Number: XC68HC08KH12
• Description: MICROCONTROLLER
• Manufacturer: Motorola

13.4 I/O Signals
13.4.1 CGMXCLK
13.4.2 COPCTL Write
MC68HC(7)08KH12
MOTOROLA
NOTE:
NOTE:
—
Rev. 1.0
The COP counter is a free-running 6-bit counter preceded by the 12-bit
SIM counter. If not cleared by software, the COP counter overflows and
generates an asynchronous reset after 2
cycles, depending on the setting of the COP rate select bit, COPRS, in
the configuration register. With a 2
option, a 6MHz crystal gives a COP timeout period of 43.688ms. Writing
any value to location $FFFF before an overflow occurs prevents a COP
reset by clearing the COP counter and stages 12 through 5 of the SIM
counter.
Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the
COP bit in the reset status register (RSR)
Register
Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
The following paragraphs describe the signals shown in
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency
is equal to the crystal frequency.
Writing any value to the COP control register (COPCTL)
Control Register
through 4 of the SIM counter. Reading the COP control register returns
the low byte of the reset vector.
Computer Operating Properly (COP)
(RSR)).
(COPCTL)) clears the COP counter and clears bits 12
18
– 2
4
18
Computer Operating Properly (COP)
CGMXCLK cycle overflow
(see 7.8.2 Reset Status
– 2
4
or 2
13
Advance Information
– 2
(see 13.5 COP
Figure
4
CGMXCLK
I/O Signals
13-1.
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