XC68HC08KH12 Motorola, XC68HC08KH12 Datasheet - Page 102

• Manufacturer Part Number: XC68HC08KH12
• Description: MICROCONTROLLER
• Manufacturer: Motorola

Clock Generator Module (CGM)
8.6.1 PLL Control Register (PCTL)
Advance Information
102
NOTE:
Address:
The PLL control register contains the interrupt enable and flag bits, the
on/off switch, the base clock selector bit, the prescaler bits, and the VCO
power of two range selector bits.
PLLIE — PLL Interrupt Enable Bit
PLLF — PLL Interrupt Flag Bit
Do not inadvertently clear the PLLF bit. Any read or read-modify-write
operation on the PLL control register clears the PLLF bit.
Reset:
Read:
Write:
This read/write bit enables the PLL to generate an interrupt request
when the LOCK bit toggles, setting the PLL flag, PLLF. When the
AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as logic zero. Reset clears the
PLLIE bit.
This read-only bit is set whenever the LOCK bit toggles. PLLF
generates an interrupt request if the PLLIE bit also is set. PLLF
always reads as logic zero when the AUTO bit in the PLL bandwidth
control register (PBWC) is clear. Clear the PLLF bit by reading the
PLL control register. Reset clears the PLLF bit.
1 = PLL interrupts enabled
0 = PLL interrupts disabled
1 = Change in lock condition
0 = No change in lock condition
$003A
PLLIE
Bit 7
0
Clock Generator Module (CGM)
Figure 8-3. PLL Control Register (PCTL)
= Unimplemented
PLLF
6
0
PLLON
5
1
BCS
4
0
PRE1
3
1
MC68HC(7)08KH12
PRE2
2
0
1
0
0
MOTOROLA
—
Rev. 1.0
Bit 0
0
0