XC68HC08KH12 Motorola, XC68HC08KH12 Datasheet - Page 140
XC68HC08KH12
Manufacturer Part Number
XC68HC08KH12
Description
MICROCONTROLLER
Manufacturer
Motorola
Datasheet
1.XC68HC08KH12.pdf
(262 pages)
- Current page: 140 of 262
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Universal Serial Bus Module (USB)
9.5.3 USB Embedded Device Interrupt Register 1 (DIR1)
Advance Information
140
Address:
TXD0FR — Embedded Device Endpoint 0 Transmit Flag Reset
RXD0FR — Embedded Device Endpoint 0 Receive Flag Reset
TXD1F — Embedded Device Endpoint 1/2 Data Transmit Flag
Reset:
Figure 9-14. USB Embedded Device Interrupt Register 1 (DIR1)
Read:
Write:
Writing a logic 1 to this write only bit will clear the TXD0F bit if it is set.
Writing a logic 0 to TXD0FR has no effect. Reset clears this bit.
Writing a logic 1 to this write only bit will clear the RXD0F bit if it is set.
Writing a logic 0 to RXD0FR has no effect. Reset clears this bit.
This read only bit is shared by Endpoint 1 and Endpoint 2 of the
embedded device. It is set after the data stored in the shared Endpoint
1/2 transmit buffer of the embedded device has been sent and an
ACK handshake packet from the host is received. Once the next set
of data is ready in the transmit buffers, software must clear this flag
by writing a logic 1 to the TXD1FR bit. To enable the next data packet
transmission, TX1E must also be set. If TXD1F bit is not cleared, a
NAK handshake will be returned in the next IN transaction. Reset
clears this bit. Writing to TXD1F has no effect.
1 = Receive Embedded Device Endpoint 0 can generate a CPU
0 = Receive Embedded Device Endpoint 0 cannot generate a CPU
TXD1F
$004A
Bit 7
Universal Serial Bus Module (USB)
interrupt request
interrupt request
0
= Unimplemented
6
0
0
5
0
0
4
0
0
TXD1IE
3
0
MC68HC(7)08KH12
2
0
0
TXD1FR
1
0
0
MOTOROLA
—
Rev. 1.0
Bit 0
0
0
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