XC68HC08KH12 Motorola, XC68HC08KH12 Datasheet - Page 173

• Manufacturer Part Number: XC68HC08KH12
• Description: MICROCONTROLLER
• Manufacturer: Motorola

11.8.2 TIM Channel I/O Pins (PTE1/TCH0:PTE2/TCH1)
11.9 I/O Registers
11.9.1 TIM Status and Control Register (TSC)
MC68HC(7)08KH12
MOTOROLA
—
Rev. 1.0
minimum TCLK pulse width, TCLK
The maximum TCLK frequency is:
PTE0/TCLK is available as a general-purpose I/O pin when not used as
the TIM clock input. When the PTE0/TCLK pin is the TIM clock input, it
is an input regardless of the state of the DDRE0 bit in data direction
register E.
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTE1/TCH0 can be configured as
buffered output compare or buffered PWM pins.
The following I/O registers control and monitor operation of the TIM:
The TIM status and control register does the following:
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TIM status and control register (TSC)
TIM control registers (TCNTH:TCNTL)
TIM counter modulo registers (TMODH:TMODL)
TIM channel status and control registers (TSC0 and TSC1)
TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)
Enables TIM overflow interrupts
Flags TIM overflows
Stops the TIM counter
Timer Interface Module (TIM)
------------------------------------ -
bus frequency
bus frequency
------------------------------------ -
1
LMIN
2
or TCLK
+
t
SU
Timer Interface Module (TIM)
HMIN
, is:
Advance Information
I/O Registers
173