AT83C24 ATMEL Corporation, AT83C24 Datasheet - Page 26

• Manufacturer Part Number: AT83C24
• Description: Smart Card Reader Interface with Power Management
• Manufacturer: ATMEL Corporation

Table 11. INTERFACE (Interface Byte)
26
Bit Number
7
0
7
6
5
4
3
2
1
0
AT83C24
Bit Mnemonic
CARDRST
CARDCK
CKSTOP
CARDC8
CARDC4
CARDIO
IODIS
IODIS
6
0
Description
This bit should not be set.
Card I/O isolation
Set this bit to drive the CIO, CC4, CC8 pins according to CARDIO, CARDC4, CARDC8 respectively and to put
I/O, C4, C8 in Hi-Z. This can be used to have the I/O, and C4 and C8 pins of the host communicating with
another AT83C24 interface, while CIO, CC4 and CC8 are driven by software (or if the card is in standby or
power-down modes).
Clear this bit to drive the I/O/CIO, C4/CC4 and C8/CC8 pins according to each other. This can be used to activate
asynchronous cards.
The reset value is 1.
CARD Clock Stop
Set this bit to stop CCLK according to CARDCK. This can be used to set asynchronous cards in power-down
mode (GSM) or to drive CCLK by software.
Clear this bit to have CCLK running according to CKS. This can be used to activate asynchronous cards.
Note:
The reset value is 1.
Card Reset
Set this bit to enter a reset sequence according to ART bit value.
Clear this bit to drive a low level on the CRST pin.
The reset value is 0.
Card C8
Set this bit to drive the CC8 pin High with the on-chip pull-up (according to IODIS bit value). The pin can then be
an input (read in STATUS register).
Clear this bit to drive a low level on the CC8 pin (according to IODIS bit value).
The reset value is 0.
Card C4
Set this bit to drive the CC4 pin High with the on-chip pull-up (according to IODIS bit value). The pin can then be
an input (read in STATUS register).
Clear this bit to drive a low level on the CC4 pin (according to IODIS bit value).
The reset value is 0.
Card Clock
Set this bit to set a high level on the CCLK pin (according to CKSTOP bit value).
Clear this bit to drive a low level on the CCLK pin.
The reset value is 0.
Card I/O
Set this bit to drive the CIO pin High with the on-chip pull-up (according to IODIS bit value). The pin can then be
an input (read in STATUS register).
Clear this bit to drive a low level on the CIO pin (according to IODIS bit value).
The reset value is 0.
CKSTOP
5
1. When this bit is changed a special logic ensures that no glitch occurs on the CCLK pin
2. CKSTOP must be set before switching on the DC/DC with VCARD[1:0].
and actual configuration changes can be delayed by half a period to two periods of
CCLK.
CARDRST
4
CARDC8
3
CARDC4
2
CARDCK
1
4234E–SCR–09/04
CARDIO
0