AT83C24 ATMEL Corporation, AT83C24 Datasheet - Page 17

• Manufacturer Part Number: AT83C24
• Description: Smart Card Reader Interface with Power Management
• Manufacturer: ATMEL Corporation

Deactivation Sequence
4234E–SCR–09/04
Note:
Note:
The card automatic deactivation is triggered when one the following condition occurs:
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It is a self-timed sequence which cannot be interrupted when started (see Figure 13).
Each step is separated by a delay based on Td equal to 8 periods of the DC/DC clock,
typically 2 µs:
Figure 12. Software activation without automatic control (ART bit = 0)
ICARDERR bit is set by hardware
VCARDERR bit is set by hardware (or by software)
INSERT is set and CARDIN is cleared (card extraction)
SHUTDOWN is set by software
CMDVCC goes from Low to High
Power fail on VCC (see POWERMON bit in CONFIG4 register)
Reset pin going low
1. T0: CARDRST is cleared, SHUTDOWN bit set.
2. T0 + 5 x Td:CARDCK is cleared, CKSTOP, CARDIO and IODIS are set.
3. T0 + 6 x Td: CARDIO is cleared.
4. T0 + 7 x Td: VCARD[1-0] = 00.
It is assumed that initially VCARD[1:0], CARDCK, CARDIO and CARDRST bits are
cleared, CKSTOP and IODIS are set (those bits are further explained in the registers
description)
The user should check the AT83C24 status and possibly resume the activation sequence
if one TWI transfer is not acknowledged during the activation sequence.
CCLK
CVCC
CRST
CIO
1
2
3
4
ATR
AT83C24
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