AT83C24 ATMEL Corporation, AT83C24 Datasheet - Page 11

• Manufacturer Part Number: AT83C24
• Description: Smart Card Reader Interface with Power Management
• Manufacturer: ATMEL Corporation

CIO, CC4, CC8 Controller
Clock Controller
4234E–SCR–09/04
The CIO, CC4, CC8 output pins are driven respectively by CARDIO, CARDC4,
CARDC8 bits values or by I/O, C4, C8 signal pins. This selection depends of the IODIS
bit value. If IODIS is reset, data are bidirectional between respectively I/O, C4, C8 pins
and CIO, CC4, CC8 pins.
IO and CIO pins are linked together through the on chip level shifters if IODIS bit=0 in
INTERFACE register. This is done automatically during an hardware activation.
Their iddle level are 1. With IO high, CIO is pulled up.
The same behavior is applicable on C4/ CC4 and C8/ CC8 pins.
The maximum frequency on those lines depends on CLK frequency (3 clock rising
edges to transfer). With CLK=27MHz, the maximum frequency on this line is 1.5MHz.
Due to the minimum transfer delay allowed for NDS applications, the CLK minimum fre-
quency is 18MHz.
The clock controller generates two clocks (as shown in Figure 6 and Figure 7):
1. a clock for the CCLK: Four different sources can be used: CLK pin, DCCLK sig-
2. a clock for DC/DC converter.
Figure 5. CIO, CC4, CC8 Block Diagram
nal, CARDCK bit or A2/CK pin (in transparent mode).
I/O
C4
C8
EVCC
EVCC
CARDIO bit
CARDC8 bit
CARDC4 bit
1
0
1
1
0
0
IODIS bit
CVCC
CVCC
CVCC
AT83C24
CC8
CIO
CC4
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