WM8351CGEB/RV WOLFSON [Wolfson Microelectronics plc], WM8351CGEB/RV Datasheet - Page 90

• Manufacturer Part Number: WM8351CGEB/RV
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

WM8351
13.10 DIGITAL AUDIO INTERFACE
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The audio interface enables the WM8351 to exchange audio data with other system components. It is
separate from the control interface and has four dedicated pins:
The LRCLK and BCLK pins are outputs when the WM8351 operates as a master device and are
inputs when it is a slave device.
In order to allow the ADC and DAC to run at different sampling rates, separate ADCLRCLK and
ADCBCLK signals are both available through GPIO pins: GPIO5 (ADCLRCLK) and GPIO6 or GPIO8
(ADCBCLK). This feature also allows mixed Master/Slave operation between the ADC and DAC.
The audio interface supports six different audio data formats:
In all of these formats, the MSB (most significant bit) of each data sample is transferred first and the
LSB (least significant bit) last.
R112 (70h)
Audio
Interface
13.10.1 AUDIO DATA FORMATS
ADDRESS
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ADCDAT: Output pin for data coming from the audio ADC
DACDAT: Input pin for audio data going to the audio DAC
LRCLK: Data Left/Right alignment clock (also known as “word clock”)
BCLK: Bit clock, for synchronisation
Left justified
Right justified
I
DSP mode A
DSP mode B
TDM Mode
2
S
11:10
BIT
15
13
12
AIF_BCLK_INV
AIF_TRI
AIF_LRCLK_IN
V
AIF_WL [1:0]
LABEL
DEFAULT
(24 bits)
10
0
0
0
BCLK polarity
0 = normal
1 = inverted
Sets Output enables for LRCLK and
BCLK and ADCDAT to inactive state
0 = normal
1 = forces pins to Hi-Z
LRCLK clock polarity
0 = normal
1 = inverted
DSP Mode – mode A/B select
0 = MSB is available on 2
edge after LRCLK rising edge (mode A)
1 = MSB is available on 1
edge after LRCLK rising edge (mode B)
Data word length
11 = 32 bits
10 = 24 bits
01 = 20 bits
00 = 16 bits
Note: When using the Right-Justified
data format (AIF_FMT=00), the
maximum word length is 24 bits.
DESCRIPTION
PD, April 2012, Rev 4.5
nd
st
Production Data
BCLK rising
BCLK rising
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