WM8351CGEB/RV WOLFSON [Wolfson Microelectronics plc], WM8351CGEB/RV Datasheet - Page 226

• Manufacturer Part Number: WM8351CGEB/RV
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

WM8351
Register 0Bh Power mgmt (4)
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REGISTER
REGISTER
ADDRESS
Power mgmt
ADDRESS
Power mgmt
R12 (0Ch)
R11 (0Bh)
(4)
(5)
BIT
BIT
12
11
10
14
13
11
10
8
5
4
3
2
9
ADC_HPF_ENA
RTC_TICK_ENA
FLL_OSC_ENA
SYSCLK_ENA
OSC32K_ENA
CODEC_ENA
TOCLK_ENA
DACR_ENA
ADCR_ENA
DACL_ENA
ADCL_ENA
CHG_ENA
FLL_ENA
LABEL
LABEL
DEFAULT
DEFAULT
0
1
0
0
0
0
0
0
0
0
1
1
1
CODEC SYSCLK enable
0 = disabled
1 = enabled
High Pass Filter enable
0 = disabled
1 = enabled
Master Enable for FLL
0 = disabled
1 = enabled
FLL OSC enable
0 = disabled
1 = enabled
Slow clock enable. Used the zero cross timeout.
0 = disabled
1 = enabled
Right DAC enable
0 = disabled
1 = enabled
Left DAC enable
0 = disabled
1 = enabled
Right ADC enable
0 = disabled
1 = enabled
When ADCR and ADCL are used together as a stereo
pair, then both ADCs must be enabled together using
a single register write to Register R11 (0Bh).
Left ADC enable
0 = disabled
1 = enabled
When ADCR and ADCL are used together as a stereo
pair, then both ADCs must be enabled together using
a single register write to Register R11 (0Bh).
Real Time Clock control.
0 = RTC is disabled
1 = RTC is enabled.
Protected by security key. Reset by state machine.
Default held in metal mask.
32kHz crystal oscillator control
0 = 32kHz OSC is disabled
1 = 32kHz OSC is enabled
Protected by security key. Reset by state machine.
Default held in metal mask.
Charger control
Master codec enable bit. Until this bit is set, all codec
registers are held in reset.
0 = All codec registers held in reset
1 = Codec registers operate normally.
Reset by state machine.
DESCRIPTION
DESCRIPTION
PD, April 2012, Rev 4.5
REFER TO
REFER TO
Production Data
226