WM8351CGEB/RV WOLFSON [Wolfson Microelectronics plc], WM8351CGEB/RV Datasheet - Page 200

• Manufacturer Part Number: WM8351CGEB/RV
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

WM8351
24.3 SECOND-LEVEL INTERRUPTS
w
The following sections define the second-level interrupt status and control bits associated with each of
the first-level bits defined in Table 142.
24.3.1
The first-level OC_INT interrupt comprises one second-level interrupt for the limit switch. This status
bit is in Register R29 and its mask bit is in Register R37, as defined in Table 143.
R29 (1Dh)
Over Current
Interrupt Status
R37 (25h)
Over Current
Interrupt Mask
Table 143 Over-Current Interrupts
The first-level UV_INT interrupt comprises several second-level interrupts for the DC-DCs and LDOs.
Each of these has a status bit in Register R28 and a mask bit in Register R36, as defined in Table
144.
R28 (1Ch)
Under Voltage
Interrupt Status
R36 (24h)
Under Voltage
Interrupt Mask
Table 144 Under Voltage Interrupts
24.3.2
ADDRESS
ADDRESS
OVERCURRENT INTERRUPTS
UNDERVOLTAGE INTERRUPTS
11:0
BIT
BIT
15
15
11
10
9
8
3
2
1
0
OC_LS_EINT
IM_OC_LS_EINT
UV_LDO4_EINT
UV_LDO3_EINT
UV_LDO2_EINT
UV_LDO1_EINT
UV_DC4_EINT
UV_DC3_EINT
UV_DC2_EINT
UV_DC1_EINT
“IM_” + name of respective bit
in R28
LABEL
LABEL
Limit Switch Over-current interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
When IM_OC_LS_EINT is set to 1, then
OC_LS_EINT in R29 does not trigger an
OC_INT interrupt when set. The default
value is 0 (unmasked).
LDO4 Under-voltage interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
LDO3 Under-voltage interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
LDO2 Under-voltage interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
LDO1 Under-voltage interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
DCDC4 Under-voltage interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
DCDC3 Under-voltage interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
DCDC2 Under-voltage interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
DCDC1 Under-voltage interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Each bit in R36 enables or masks the
corresponding bit in R28. The default
value for these bits is 0 (unmasked).
DESCRIPTION
DESCRIPTION
PD, April 2012, Rev 4.5
Production Data
200