WM8351CGEB/RV WOLFSON [Wolfson Microelectronics plc], WM8351CGEB/RV Datasheet - Page 32

• Manufacturer Part Number: WM8351CGEB/RV
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

WM8351
10 SIGNAL TIMING REQUIREMENTS
10.1 SYSTEM CLOCK TIMING
10.2 AUDIO INTERFACE TIMING - MASTER MODE
w
Master Clock Timing
PARAMETER
MCLK cycle time
MCLK duty cycle
Test Conditions
DCVDD = 1.8V, DBVDD = 3.3V, DGND = 0V, T
PARAMETER
BCLK rise time (10pF load)
BCLK fall time (10pF load)
BCLK duty cycle
LRC propagation delay from BCLK falling edge
ADCDAT propagation delay from BCLK falling edge
DACDAT setup time to BCLK rising edge
DACDAT hold time from BCLK rising edge
Figure 14 Master Clock Timing
Figure 15 Digital Audio Data Timing – Master Mode
SYMBOL
T
MCLKY
A
= +25
= high time / low time
TEST CONDITIONS
o
C, Master Mode, fs = 48kHz, 24-bit data, unless otherwise stated.
SYMBOL
t
t
t
BCLKDS
BCLKR
BCLKF
t
t
t
t
DDA
DST
DHT
DL
60:40
MIN
40
60:40
MIN
10
10
TYP
TYP
PD, April 2012, Rev 4.5
40:60
MAX
40:60
MAX
10
10
3
3
Production Data
UNIT
UNIT
ns
ns
ns
ns
ns
ns
ns
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