LM3S101-IRN20 ETC2 [List of Unclassifed Manufacturers], LM3S101-IRN20 Datasheet - Page 66
![no-image](/images/no-image-200.jpg)
LM3S101-IRN20
Manufacturer Part Number
LM3S101-IRN20
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S101-IRN20.pdf
(300 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LM3S101-IRN20C0X
Manufacturer:
LUMINARYM
Quantity:
20 000
- Current page: 66 of 300
- Download datasheet (2Mb)
System Control
66
Reset
Reset
Type
Type
Bit/Field
31:7
Raw Interrupt Status (RIS)
Offset 0x050
6
5
4
3
2
1
0
RO
RO
31
15
0
0
Register 13: Raw Interrupt Status (RIS), offset 0x050
Central location for system control raw interrupts. These are set and cleared by hardware.
RO
RO
30
14
0
0
PLLFRIS
PLLLRIS
reserved
MOFRIS
BORRIS
LDORIS
IOFRIS
CLRIS
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
RO
RO
25
0
9
0
0
0
0
0
0
0
0
0
Preliminary
RO
RO
24
0
8
0
reserved
Description
Reserved bits return an indeterminate value, and should
never be changed.
PLL Lock Raw Interrupt Status
This bit is set when the PLL T
Current Limit Raw Interrupt Status
This bit is set if the LDO’s CLE output asserts.
Internal Oscillator Fault Raw Interrupt Status
This bit is set if an internal oscillator fault is detected.
Main Oscillator Fault Raw Interrupt Status
This bit is set if a main oscillator fault is detected.
LDO Power Unregulated Raw Interrupt Status
This bit is set if a LDO voltage is unregulated.
Brown-Out Reset Raw Interrupt Status
This bit is the raw interrupt status for any brown-out
conditions. If set, a brown-out condition was detected. An
interrupt is reported if the BORIM bit in the IMC register is
set and the BORIOR bit in the PBORCTL register is cleared.
PLL Fault Raw Interrupt Status
This bit is set if a PLL fault is detected (stops oscillating).
RO
RO
23
0
7
0
PLLLRIS
RO
RO
22
0
6
0
CLRIS
RO
RO
21
0
5
0
IOFRIS MOFRIS LDORIS BORRIS PLLFRIS
RO
RO
20
0
4
0
READY
RO
RO
19
0
3
0
Timer asserts.
RO
RO
18
0
2
0
October 5, 2006
RO
RO
17
0
1
0
RO
RO
16
0
0
0
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