LM3S101-IRN20 ETC2 [List of Unclassifed Manufacturers], LM3S101-IRN20 Datasheet - Page 20
LM3S101-IRN20
Manufacturer Part Number
LM3S101-IRN20
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S101-IRN20.pdf
(300 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LM3S101-IRN20C0X
Manufacturer:
LUMINARYM
Quantity:
20 000
- Current page: 20 of 300
- Download datasheet (2Mb)
Architectural Overview
1.2
20
Target Applications
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GPIOs
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Power
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Flexible Reset Sources
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Additional Features
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Industrial-range 28-pin RoHS-compliant SOIC package
Factory automation and control
Compare external pin input to external pin input or to internal programmable voltage
reference
2 to 18 GPIOs, depending on configuration
5-V-tolerant input/outputs
Programmable interrupt generation as either edge-triggered or level-sensitive
Bit masking in both read and write operations through address lines
Programmable control for GPIO pad configuration:
•
•
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On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
Low-power options on controller: Sleep and Deep-sleep modes
Low-power options for peripherals: software controls shutdown of individual peripherals
User-enabled LDO unregulated voltage detection and automatic reset
3.3-V supply brownout detection and reporting via interrupt or reset
Power-on reset (POR)
Reset pin assertion
Brown-out (BOR) detector alerts to system power drops
Software reset
Watchdog timer reset
Internal low drop-out (LDO) regulator output goes unregulated
Six reset sources
Programmable clock source control
Clock gating to individual peripherals for power savings
IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
Debug access via JTAG and Serial Wire interfaces
Full JTAG boundary scan
Weak pull-up or pull-down resistors
2-mA, 4-mA, and 8-mA pad drive
Slew rate control for the 8-mA drive
Open drain enables
Digital input enables
Preliminary
October 5, 2006
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