LM3S101-IRN20 ETC2 [List of Unclassifed Manufacturers], LM3S101-IRN20 Datasheet - Page 274

• Manufacturer Part Number: LM3S101-IRN20
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Signal Tables
15
Table 15-1. Signals by Pin Number (Sheet 1 of 2)
274
Number
Pin
10
12
13
11
1
2
3
4
5
6
7
8
9
Signal Tables
The following tables list the signals available for each pin. Functionality is enabled by software with
the GPIOAFSEL register (see page 114).
Important:
Table 15-1 shows the pin-to-signal-name mapping, including functional characteristics of the
signals. Table 15-2 lists the signals in alphabetical order by signal name. Table 15-3 groups the
signals by functionality, except for GPIOs. Table 15-4 lists the GPIO pins and their alternate
functionality.
Signal Name
PB7
TRST
PB6
C0+
PB5
C0o
C1–
PB4
C0–
RST
LDO
VDD
GND
OSC0
OSC1
PA0
U0Rx
PA1
U0Tx
PA2
SSIClk
All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins
(PB7 and PC[3:0]) which default to the JTAG functionality.
Type
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
I
I
I
-
-
-
I
I
Analog
Analog
Analog
Analog
Analog
Buffer
Power
Power
Power
Type
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Preliminary
Description
GPIO port B bit 7.
JTAG TAP reset input.
GPIO port B bit 6.
Analog comparator 0 positive reference input.
GPIO port B bit 5.
Analog comparator 0 output.
Analog comparator 1 negative reference input.
GPIO port B bit 4.
Analog comparator 0 negative reference input.
System reset input.
The low drop-out regulator output voltage. This pin requires an
external capacitor between the pin and GND of 1 μF or greater.
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
Oscillator crystal output.
GPIO port A bit 0.
UART0 receive data input.
GPIO port A bit 1.
UART0 transmit data output.
GPIO port A bit 2.
master mode).
Oscillator crystal input or an external clock reference input.
SSI clock reference (input when in slave mode and output in
October 5, 2006