LM3S101-IRN20 ETC2 [List of Unclassifed Manufacturers], LM3S101-IRN20 Datasheet - Page 33
LM3S101-IRN20
Manufacturer Part Number
LM3S101-IRN20
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S101-IRN20.pdf
(300 pages)
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Part Number
Manufacturer
Quantity
Price
Part Number:
LM3S101-IRN20C0X
Manufacturer:
LUMINARYM
Quantity:
20 000
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October 5, 2006
Table 4-1. Exception Types (Continued)
a. 0 is the default priority for all the settable priorities.
Table 4-2. Interrupts
Exception Type
Usage Fault
-
SVCall
Debug Monitor
-
PendSV
SysTick
Interrupts
(Bit in Interrupt Registers)
Interrupt
8-17
3-4
18
19
20
21
22
0
1
2
5
6
7
Position
16 and
above
7
12
13
14
15
11
-
6
10
Description
GPIO Port A
GPIO Port B
GPIO Port C
Reserved
UART0
Reserved
SSI
Reserved
Watchdog timer
Timer0a
Timer0b
Timer1a
Timer1b
Priority
settable
settable
settable
settable
settable
settable
Preliminary
-
-
a
Description
Usage fault, such as undefined instruction executed
or illegal state transition attempt. This is
synchronous.
Reserved.
System service call with SVC instruction. This is
synchronous.
Debug monitor (when not halting). This is
synchronous, but only active when enabled. It does
not activate if lower priority than the current
activation.
Reserved.
Pendable request for system service. This is
asynchronous and only pended by software.
System tick timer has fired. This is asynchronous.
Asserted from outside the ARM Cortex
fed through the NVIC (prioritized). These are all
asynchronous. Table 4-2 lists the interrupts on the
LM3S101 controller.
LM3S101 Data Sheet
-
M3 core and
33
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