LM3S101-IRN20 ETC2 [List of Unclassifed Manufacturers], LM3S101-IRN20 Datasheet - Page 271
![no-image](/images/no-image-200.jpg)
LM3S101-IRN20
Manufacturer Part Number
LM3S101-IRN20
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S101-IRN20.pdf
(300 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LM3S101-IRN20C0X
Manufacturer:
LUMINARYM
Quantity:
20 000
- Current page: 271 of 300
- Download datasheet (2Mb)
October 5, 2006
Reset
Reset
Type
Type
Bit/Field
31:11
10:9
Analog Comparator Control 0 (ACCTL0)
Offset 0x024
8:5
3:2
4
RO
RO
31
15
0
0
Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x24
Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x44
These registers configure that comparator’s input and output.
RO
RO
30
14
0
0
reserved
reserved
ASRCP
ISLVAL
Name
ISEN
reserved
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
R/W
R/W
R/W
RO
RO
RO
RO
27
11
0
0
R/W
RO
RO
26
10
0
0
0
ASRCP
Reset
0
0
0
0
0
R/W
RO
RO
25
0
9
0
0
Preliminary
RO
RO
RO
24
Description
Reserved bits return an indeterminate value, and should
never be changed.
The ASRCP field specifies the source of input voltage to the
VIN+ terminal of the comparator. The encodings for this field
are as follows:
Reserved bits return an indeterminate value, and should
never be changed.
The ISLVAL bit specifies the sense value of the input that
generates an interrupt if in Level Sense mode. If 0, an
interrupt is generated if the comparator output is Low.
Otherwise, an interrupt is generated if the comparator output
is High.
The ISEN field specifies the sense of the comparator output
that generates an interrupt. The sense conditioning is as
follows:
0
8
0
0
reserved
ASRCP
00
01
10
11
ISEN
00
01
10
11
RO
RO
RO
23
0
7
0
0
reserved
Function
Pin value
Pin value of C0+
Internal voltage reference
Reserved
RO
RO
RO
22
0
6
0
0
Function
Level sense, see ISLVAL
Falling edge
Rising edge
Either edge
RO
RO
RO
21
0
5
0
0
ISLVAL
R/W
RO
RO
20
0
4
0
0
R/W
RO
RO
19
0
3
0
0
ISEN
LM3S101 Data Sheet
R/W
RO
RO
18
0
2
0
0
CINV
R/W
RO
RO
17
0
1
0
0
reserved
RO
RO
RO
16
0
0
0
0
271
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