LM3S101-IRN20 ETC2 [List of Unclassifed Manufacturers], LM3S101-IRN20 Datasheet - Page 39
LM3S101-IRN20
Manufacturer Part Number
LM3S101-IRN20
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S101-IRN20.pdf
(300 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LM3S101-IRN20C0X
Manufacturer:
LUMINARYM
Quantity:
20 000
- Current page: 39 of 300
- Download datasheet (2Mb)
Figure 5-2. Test Access Port State Machine
5.2.3
5.2.4
5.2.4.1
October 5, 2006
Shift Registers
The Shift Registers consist of a serial shift register chain and a parallel load register. The serial
shift register chain samples specific information during the TAP controller’s CAPTURE states and
allows this information to be shifted out of TDO during the TAP controller’s SHIFT states. While the
sampled data is being shifted out of the chain on TDO, new data is being shifted into the serial shift
register on TDI. This new data is stored in the parallel load register during the TAP controller’s
UPDATE states. Each of the shift registers is discussed in detail in “Shift Registers” on page 39.
Operational Considerations
There are certain operational considerations when using the JTAG module. Because the JTAG
pins can be programmed to be GPIOs, board configuration and reset conditions on these pins
must be considered. In addition, because the JTAG module has integrated ARM Serial Wire
Debug, the method for switching between these two operational modes requires clarification.
GPIO Functionality
When the controller is reset with either a POR or RST, the JTAG port pins default to their JTAG
configurations. The default configuration includes enabling the pull-up resistors (setting GPIOPUR
1
0
Run Test Idle
Test Logic
0
1
1
0
Preliminary
Select DR Scan
Capture DR
Update DR
Pause DR
Exit 1 DR
Exit 2 DR
Shift DR
1
0
0
1
0
1
1
0
1
0
1
0
1
0
Select IR Scan
Capture IR
Update IR
Pause IR
Exit 1 IR
Exit 2 IR
Shift IR
LM3S101 Data Sheet
1
0
0
1
0
1
1
0
1
0
1
0
39
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