MC9S12E32CFU FREESCALE [Freescale Semiconductor, Inc], MC9S12E32CFU Datasheet - Page 63

• Manufacturer Part Number: MC9S12E32CFU
• Description: HCS12 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

1
If the port pins are not bonded out in the chosen package the user should initialize the registers to be inputs
with enabled pull resistance to avoid excess current consumption. This applies to the following pins:
Freescale Semiconductor
Function 1
Pin Name
The Port E output buffer enable signal control at reset is determined by the PEAR register and is mode dependent. For
example, in special test mode RDWE = LSTRE = 1 which enables the PE[3:2] output buffers and disables the pull-ups. Refer
to the S12 MEBI block description chapter for PEAR register details.
PQ[6:4]
PQ[3:0]
PU[7:6]
PU[5:4]
PP[5:0]
PU[3:0]
PT[7:4]
PT[3:0]
PM0
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
(80QFP): Port A[7:0], Port B[7:0], Port E[6,5,3,2], Port K[7:0], Port U[7:4]
(64QFN): Port U[3:0], Port Q[6:4], Port M[3], Port AD[14,11,10,9,7,5,3,1]
Function 2
FAULT[3:0]
Pin Name
IOC1[7:4]
IOC0[7:4]
PW1[5:4]
IOC2[7:4]
PW0[5:0]
Signals shown in bold are not available in the 112-pin package.
Signals shown in italic are not available in the 80-pin package.
IS[6:4]
RXD1
RXD0
DAO0
MOSI
MISO
TXD1
TXD0
SCK
SS
—
Function 3
Pin Name
PW1[3:0]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MC9S12E128 Data Sheet, Rev. 1.07
Domain
Table 1-4. Signal Properties
Power
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
PERM/
PERQ/
PERQ/
PERP/
PERS/
PERS/
PERS/
PERS/
PERS/
PERS/
PERS/
PERS/
PERU/
PERU/
PERU/
PPSM
PERT/
PERT/
CTRL
PPSP
PPSQ
PPSQ
PPSS
PPSS
PPSS
PPSS
PPSS
PPSS
PPSS
PPSS
PPSU
PPSU
PPSU
Internal Pull Resistor
PPST
PPST
NOTE
Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1)
Reset State
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Up
Up
Up
Up
Up
Up
Up
Up
Port M I/O Pin, DAC0 output
Port P I/O Pins, PWM output
Port Q I/O Pins, IS[6:4] input
Port Q I/O Pins, Fault[3:0] input
Port S I/O Pin, SPI SS signal
Port S I/O Pin, SPI SCK signal
Port S I/O Pin, SPI MOSI signal
Port S I/O Pin, SPI MISO signal
Port S I/O Pin, SCI1 transmit signal
Port S I/O Pin, SCI1 receive signal
Port S I/O Pin, SCI0 transmit signal
Port S I/O Pin, SCI0 receive signal
Port T I/O Pins, timer (TIM1)
Port T I/O Pins, timer (TIM0)
Port U I/O Pins
Port U I/O Pins, PWM outputs
Port U I/O Pins, timer (TIM2), PWM
outputs
Description
63