MC9S12E32CFU FREESCALE [Freescale Semiconductor, Inc], MC9S12E32CFU Datasheet - Page 432

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MC9S12E32CFU

Manufacturer Part Number
MC9S12E32CFU
Description
HCS12 Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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Chapter 13 Timer Module (TIM16B4CV1)
For the description of PACLK please refer
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an
input clock to the timer counter. The change from one selected clock to the other happens immediately
after these bits are written.
432
PAOVI
Field
PAI
1
0
Pulse Accumulator Overflow Interrupt Enable
0 Interrupt inhibited.
1 Interrupt requested if PAOVF is set.
Pulse Accumulator Input Interrupt Enable
0 Interrupt inhibited.
1 Interrupt requested if PAIF is set.
If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64
because the 64 clock is generated by the timer prescaler.
PAMOD
CLK1
0
0
1
1
0
0
1
1
Table 13-17. PACTL Field Descriptions (continued)
PEDGE
CLK0
0
1
0
1
0
1
0
1
Table 13-19. Timer Clock Selection
MC9S12E128 Data Sheet, Rev. 1.07
Table 13-18. Pin Action
Use PACLK/65536 as timer counter clock frequency
Use PACLK/256 as timer counter clock frequency
Figure
Use timer prescaler clock as timer counter clock
Div. by 64 clock enabled with pin high level
Use PACLK as input to timer counter clock
Div. by 64 clock enabled with pin low level
NOTE
13-22.
Description
Timer Clock
Falling edge
Rising edge
Pin Action
Freescale Semiconductor

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