MC9S12E32CFU FREESCALE [Freescale Semiconductor, Inc], MC9S12E32CFU Datasheet - Page 137

• Manufacturer Part Number: MC9S12E32CFU
• Description: HCS12 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

3.3.2
Port M is associated with the serial communication interface (SCI2) , Inter-IC bus (IIC) and the digital to
analog converter (DAC0 and DAC1) modules. Each pin is assigned to these modules according to the
following priority: IIC/SCI2/DAC1/DAC0 > general-purpose I/O.
When the IIC bus is enabled, the PM[7:6] pins become SCL and SDA respectively. Refer to the IIC block
description chapter for information on enabling and disabling the IIC bus.
When the SCI2 receiver and transmitter are enabled, the PM[5:4] become RXD2 and TXD2 respectively.
Refer to the SCI block description chapter for information on enabling and disabling the SCI receiver and
transmitter.
When the DAC1 and DAC0 outputs are enabled, the PM[1:0] become DAO1 and DAO0 respectively.
Refer to the DAC block description chapter for information on enabling and disabling the DAC output.
During reset, PM[3] and PM[1:0] pins are configured as high-impedance inputs and PM[7:4] pins are
configured as pull-up inputs.
3.3.2.1
Read: Anytime. Write: Anytime.
If the associated data direction bit (DDRMx) is set to 1 (output), a read returns the value of the I/O register
bit. If the associated data direction bit (DDRMx) is set to 0 (input), a read returns the value of the pin.
3.3.2.2
Freescale Semiconductor
DAC1/DAC0:
Reset
Reset
SCI2:
W
R
IIC:
W
R
PTIM7
Port M
Port M I/O Register (PTM)
Port M Input Register (PTIM)
u
7
PTM7
SCL
0
7
= Reserved or Unimplemented
= Reserved or Unimplemented
PTIM6
u
6
PTM6
SDA
0
6
Figure 3-11. Port M Input Register (PTIM)
Figure 3-10. Port M I/O Register (PTM)
PTIM5
MC9S12E128 Data Sheet, Rev. 1.07
u
5
PTM5
TXD2
0
5
PTIM4
PTM4
u
RXD2
4
0
4
u = Unaffected by reset
PTIM3
PTM3
u
3
0
3
Chapter 3 Port Integration Module (PIM9E128V1)
0
0
2
0
0
2
PTIM1
PTM1
DAO1
u
1
0
1
PTIM0
PTM0
DAO0
u
0
0
0
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