MC9S12E32CFU FREESCALE [Freescale Semiconductor, Inc], MC9S12E32CFU Datasheet - Page 574

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MC9S12E32CFU

Manufacturer Part Number
MC9S12E32CFU
Description
HCS12 Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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Appendix A Electrical Characteristics
A.3
A.3.1
Table A-11
A.3.1.1
The release level V
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t
clock. The fastest startup time possible is given by n
A.3.1.2
The release level V
if the device is powered externally. After releasing the LVR reset the oscillator and the clock quality check
are started. If after a time t
clock. The fastest startup time possible is given by n
A.3.1.3
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.
574
Conditions are shown in
Num
1
2
3
4
5
6
7
8
Startup, Oscillator and PLL
C
D
D
D
D
P
P
T
T
summarizes several startup characteristics explained in this section.
Startup
POR
LVR
SRAM Data Retention
POR release level
POR assert level
Reset input pulse width, minimum input time
Startup from Reset
Interrupt pulse width, IRQ edge-sensitive
mode
Wait recovery startup time
LVR release level
LVR assert level
PORR
LVRR
Table A-4
and the assert level V
and the assert level V
CQOUT
CQOUT
unless otherwise noted
Rating
no valid oscillation is detected, the MCU will start using the internal self
no valid oscillation is detected, the MCU will start using the internal self
Table A-11. Startup Characteristics
MC9S12E128 Data Sheet, Rev. 1.07
LVRA
PORA
are derived from the V
are derived from the V
uposc
uposc
.
.
Symbol
PW
V
V
PW
V
V
n
t
PORR
PORA
WRS
LVRR
LVRA
RST
RSTL
IRQ
Min
0.97
2.25
192
20
2
DD
DD
Supply. They are also valid
Supply. They are also valid
Typ
Freescale Semiconductor
Max
2.07
2.55
196
14
Unit
n
t
t
ns
osc
cyc
V
V
osc
V
V

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