DSPIC30F6010A MICROCHIP [Microchip Technology], DSPIC30F6010A Datasheet - Page 18

• Manufacturer Part Number: DSPIC30F6010A
• Description: High-Performance, 16-bit Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

dsPIC30F6010A/6015
2.3
The dsPIC DSC devices feature a 16/16-bit signed
fractional divide operation, as well as 32/16-bit and
16/16-bit signed and unsigned integer divide opera-
tions, in the form of single instruction iterative divides.
The following instructions and data sizes are
supported:
• DIVF – 16/16 signed fractional divide
• DIV.sd – 32/16 signed divide
• DIV.ud – 32/16 unsigned divide
• DIV.s – 16/16 signed divide
• DIV.u – 16/16 unsigned divide
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g., a
series of discrete divide instructions) will not function
correctly because the instruction flow depends on
RCOUNT. The divide instruction does not automatically
set up the RCOUNT value, and it must, therefore, be
explicitly and correctly specified in the REPEAT instruc-
tion, as shown in
target instruction {operand value + 1} times). The
REPEAT loop count must be set up for 18 iterations of
the DIV/DIVF instruction. Thus, a complete divide
operation requires 19 cycles.
TABLE 2-2:
DS70150E-page 18
DIVF
DIV.sd
DIV.s
DIV.ud
DIV.u
Note:
Divide Support
The divide flow is interruptible. However,
the user needs to save the context as
appropriate.
Instruction
DIVIDE INSTRUCTIONS
Table 2-2
(REPEAT will execute the
Signed fractional divide: Wm/Wn → W0; Rem → W1
Signed divide: (Wm+1:Wm)/Wn → W0; Rem → W1
Signed divide: Wm/Wn → W0; Rem → W1
Unsigned divide: (Wm+1:Wm)/Wn → W0; Rem → W1
Unsigned divide: Wm/Wn → W0; Rem → W1
2.4
The DSP engine consists of a high-speed 17-bit x
17-bit multiplier, a barrel shifter, and a 40-bit adder/sub-
tractor (with two target accumulators, round and
saturation logic).
The dsPIC30F devices have a single instruction flow
which can execute either DSP or MCU instructions.
Many of the hardware resources are shared between
the DSP and MCU instructions. For example, the
instruction set has both DSP and MCU multiply
instructions which use the same hardware multiplier.
The DSP engine also has the capability to perform inher-
ent
require no additional data. These instructions are ADD,
SUB and NEG.
The DSP engine has various options selected through
various bits in the CPU Core Configuration register
(CORCON), as listed below:
1.
2.
3.
4.
5.
6.
7.
A block diagram of the DSP engine is shown in
Figure
TABLE 2-1:
Note:
Fractional or Integer DSP Multiply (IF).
Signed or Unsigned DSP Multiply (US).
Conventional or Convergent Rounding (RND).
Automatic Saturation On/Off for AccA (SATA).
Automatic Saturation On/Off for AccB (SATB).
Automatic Saturation On/Off for Writes to Data
Memory (SATDW).
Accumulator
(ACCSAT).
Instruction
accumulator-to-accumulator
MOVSAC
2-2.
MPY.N
EDAC
CLR
MAC
MPY
MSC
DSP Engine
ED
Function
For CORCON layout, see
DSP INSTRUCTION
SUMMARY
Saturation
© 2011 Microchip Technology Inc.
Algebraic Operation
A = 0
A = (x – y)
A = A + (x – y)
A = A + (x * y)
No change in A
A = x * y
A = – x * y
A = A – x * y
mode
operations,
Table
2
Selection
3-3.
2
which