DSPIC30F6010A MICROCHIP [Microchip Technology], DSPIC30F6010A Datasheet - Page 111

• Manufacturer Part Number: DSPIC30F6010A
• Description: High-Performance, 16-bit Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

17.0
The Inter-Integrated Circuit™ (I
complete hardware support for both Slave and Multi-
Master modes of the I
standard, with a 16-bit interface.
This module offers the following key features:
• I
• I
• I
• I
• Serial clock synchronization for I
• I
17.1
The hardware fully implements all the master and
slave functions of the I
specifications, as well as 7 and 10-bit addressing.
Thus, the I
a master on an I
FIGURE 17-1:
© 2011 Microchip Technology Inc.
Note:
operation.
addressing.
master and slaves.
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).
collision and will arbitrate accordingly.
2
2
2
2
2
C Slave mode supports 7-bit and 10-bit addressing.
C interface supporting both Master and Slave
C Master mode supports 7-bit and 10-bit
C port allows bidirectional transfers between
C supports multi-master operation; detects bus
I
Operating Function Description
2
2
C™ MODULE
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
C module can operate either as a slave or
2
C bus.
bit 15
bit 15
PROGRAMMER’S MODEL
2
C Standard and Fast mode
2
C serial communication
2
C™) module provides
2
C port can be
bit 9
bit 8
bit 7
bit 7
dsPIC30F6010A/6015
17.1.1
The following types of I
• I
• I
• I
See the I
17.1.2
I
is data.
17.1.3
I2CCON and I2CSTAT are control and STATUS regis-
ters, respectively. The I2CCON register is readable and
writable. The lower 6 bits of I2CSTAT are read-only.
The remaining bits of the I2CSTAT are read/write.
I2CRSR is the shift register used for shifting data,
whereas I2CRCV is the buffer register to which data
bytes are written, or from which data bytes are read.
I2CRCV is the receive buffer, as shown in Figure 16-1.
I2CTRN is the transmit register to which bytes are written
during a transmit operation, as shown in Figure 16-2.
The I2CADD register holds the slave address. A Status
bit, ADD10, indicates 10-bit Address mode. The
I2CBRG acts as the Baud Rate Generator reload
value.
In receive operations, I2CRSR and I2CRCV together
form a double-buffered receiver. When I2CRSR receives
a complete byte, it is transferred to I2CRCV and an inter-
rupt pulse is generated. During transmission, the
I2CTRN is not double-buffered.
2
C has a 2-pin interface; pin SCL is clock and pin SDA
Note:
2
2
2
C Slave operation with 7-bit addressing
C Slave operation with 10-bit addressing
C Master operation with 7-bit or 10-bit addressing
bit 0
bit 0
bit 0
bit 0
bit 0
bit 0
2
C programmer’s model in
VARIOUS I
PIN CONFIGURATION IN I
I
Following a Restart condition in 10-bit
mode, the user only needs to match the
first 7-bit address.
2
C REGISTERS
I2CRCV (8 bits)
I2CTRN (8 bits)
I2CBRG (9 bits)
I2CCON (16 bits)
I2CSTAT (16 bits)
I2CADD (10 bits)
2
C operation are supported:
2
C MODES
DS70150E-page 111
Figure
2
17-1.
C MODE