DSPIC30F6010A MICROCHIP [Microchip Technology], DSPIC30F6010A Datasheet - Page 156

• Manufacturer Part Number: DSPIC30F6010A
• Description: High-Performance, 16-bit Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

generate a clock failure trap event and will switch the sys-
dsPIC30F6010A/6015
21.2.6
The LPRC oscillator is a component of the Watchdog
Timer (WDT) and oscillates at a nominal frequency of
512 kHz. The LPRC oscillator is the clock source for
the Power-up Timer (PWRT) circuit, WDT and clock
monitor circuits. It may also be used to provide a low
frequency clock source option for applications where
power consumption is critical, and timing accuracy is
not required.
The LPRC oscillator is always enabled at a Power-on
Reset, because it is the clock source for the PWRT.
After the PWRT expires, the LPRC oscillator will remain
ON if one of the following is TRUE:
• The Fail-Safe Clock Monitor is enabled
• The WDT is enabled
• The LPRC oscillator is selected as the system
If one of the above conditions is not true, the LPRC will
shut-off after the PWRT expires.
21.2.7
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by appropriately
programming the FCKSM Configuration bits (Clock
Switch and Monitor Selection bits) in the F
Configuration register. If the FSCM function is
enabled, the LPRC internal oscillator will run at all
times (except during Sleep mode) and will not be
subject to control by the SWDTEN bit.
In the event of an oscillator failure, the FSCM will
tem clock over to the FRC oscillator. The user will then
have the option to either attempt to restart the oscillator
or execute a controlled shutdown. The user may decide
to treat the trap as a warm Reset by simply loading the
Reset address into the oscillator fail trap vector. In this
event, the CF (Clock Fail) Status bit (OSCCON<3>) is
also set whenever a clock failure is recognized.
In the event of a clock failure, the WDT is unaffected
and continues to run on the LPRC clock.
If the oscillator has a very slow start-up time coming
out of POR, BOR or Sleep, it is possible that the
PWRT timer will expire before the oscillator has
started. In such cases, the FSCM will be activated and
the FSCM will initiate a clock failure trap, and the
DS70150E-page 156
clock via the COSC<2:0> control bits in the
OSCCON register
Note 1: OSC2 pin function is determined by the
2: Note that OSC1 pin cannot be used as an
LOW-POWER RC OSCILLATOR
(LPRC)
FAIL-SAFE CLOCK MONITOR
Primary
(FPR<4:0>).
I/O pin, even if the secondary oscillator or
an internal clock source is selected at all
times.
Oscillator
mode
OSC
selection
device
COSC<2:0> bits are loaded with FRC oscillator selec-
tion. This will effectively shut-off the original oscillator
that was trying to start.
The user may detect this situation and restart the
oscillator in the clock fail trap ISR.
Upon a clock failure detection, the FSCM module will
initiate a clock switch to the FRC oscillator as follows:
1.
2.
3.
For the purpose of clock switching, the clock sources
are sectioned into four groups:
• Primary
• Secondary
• Internal FRC
• Internal LPRC
The user can switch between these functional groups,
but cannot switch between options within a group. If the
primary group is selected, then the choice within the
group is always determined by the FPR<4:0>
Configuration bits.
The OSCCON register holds the control and Status bits
related to clock switching.
• COSC<2:0>: Read-only Status bits always reflect
• NOSC<2:0>: Control bits which are written to
• LOCK: The LOCK Status bit indicates a PLL lock.
• CF: Read-only Status bit indicating if a clock fail
• OSWEN: Control bit changes from a ‘0’ to a ‘1’
If Configuration bits FCKSM<1:0> = 1x, then the clock
switching and Fail-Safe Clock Monitor functions are
disabled. This is the default Configuration bit setting.
If clock switching is disabled, then the FOS<2:0> and
FPR<4:0> bits directly control the oscillator selection
and the COSC<2:0> bits do not control the clock
selection. However, these bits will reflect the clock
source selection.
the current oscillator group in effect.
indicate the new oscillator group of choice.
- On POR and BOR, COSC<2:0> and
detect has occurred.
when a clock transition sequence is initiated.
Clearing the OSWEN control bit will abort a clock
transition in progress (used for hang-up situations).
Note:
The COSC bits (OSCCON<14:12>) are loaded
with the FRC oscillator selection value.
CF bit is set (OSCCON<3>).
OSWEN control bit (OSCCON<0>) is cleared.
NOSC<2:0> are both loaded with the
Configuration bit values FOS<2:0>.
The application should not attempt to
switch to a clock of frequency lower than
100 kHz when the Fail-Safe Clock Monitor
is enabled. If clock switching is performed,
the device may generate an oscillator fail
trap and switch to the fast RC oscillator.
© 2011 Microchip Technology Inc.